Digital Computer Architecture

Course Description

Digital Computer Architecture covers the use of electronic digital modules to design computers, the organization and operation of computers, hardware/software trade-offs, and the design of computer interfacing.

Within the SCNS taxonomy, EEL is the Electrical Engineering prefix. The University of West Florida publishes this at 3 semester hours through the Department of Electrical and Computer Engineering, College of Science and Engineering. Institutions carrying the integrated EEL4713C offer it at approximately 4 Florida institutions.

⚠ The SCNS title for this number is "Computer Architecture"; UWF publishes it as "Digital Computer Architecture." A minor difference, though it hints at the orientation — this is architecture approached as a digital design problem, following EEL4712 rather than a computer science systems course. Carry a syllabus when transferring.

The phrase to notice in the description is "hardware/software trade-offs," because that is what distinguishes architecture from digital design. EEL4712 asks how to build a circuit that does something. This course asks a harder question: given a fixed budget of transistors and a set of programs people actually run, what should the machine do in hardware and what should it leave to software? Instruction set design, caching, and pipelining are all answers to that question, and each answer has a cost.

The organising insight is that architecture is driven by measurement, not elegance. Amdahl's law — that speeding up part of a computation limits total gain to the fraction it occupies — is the discipline's governing constraint, and it is why architects profile before they optimise.

⚠ Why this guide exists under this number

Many Florida institutions carry this material as a single integrated course with a C suffix. UWF instead runs a separate lecture and a separate laboratory, each with its own SCNS number, and this guide documents the UWF lecture. Its laboratory partner is documented separately in this repository. ⚠ SCNS equivalency does not cross numbers, so a transfer between the integrated and split forms is evaluated by hand rather than automatically — carry a syllabus in either direction.

⚠ The contact-hour figure is derived — the University of West Florida publishes none

UWF's catalog publishes a credit value in semester hours, the college and department, prerequisites, and a description. It does not publish contact hours, a lecture and laboratory split, or terms of offering for any course. It does publish a material and supply fee notice on the minority of courses that carry one — and maintains a separate Material & Supply and Equipment Fees section of the catalog — so the absence of a fee notice on this entry is meaningful, while the fee amount is not published here. Every contact-hour value in a UWF guide in this repository is therefore derived. The figure here applies the standard lecture convention of 15 contact hours per credit, giving 45 hours for a 3-semester-hour course. Confirm the meeting schedule with the department.

Learning Outcomes

Required Outcomes

• Describe the major components of a computer system and their interaction.
• Describe instruction set architecture and the distinction from microarchitecture.
• Compare RISC and CISC design philosophies and their trade-offs.
• Describe addressing modes and instruction formats.
• Analyse the hardware and software trade-offs in instruction set design.
• Design a single-cycle datapath and its control unit.
• Design a multi-cycle datapath and compare it with single-cycle.
• Describe pipelining and the stages of a classic pipeline.
• Identify structural, data, and control hazards.
• Apply forwarding, stalling, and branch prediction to resolve hazards.
• Compute performance using the CPU performance equation.
• Apply Amdahl's law to evaluate a proposed optimisation.
• Describe the memory hierarchy and the principle of locality.
• Analyse cache organisation, mapping, replacement, and write policy.
• Compute average memory access time and evaluate cache performance.
• Describe virtual memory, paging, and address translation.
• Describe input and output organisation, interrupts, and direct memory access.
• Describe bus structures and interfacing.
• Describe arithmetic unit implementation and number representation effects.
• Evaluate an architectural design against quantitative performance data.

Optional Outcomes

• Describe superscalar and out-of-order execution.
• Describe multicore architecture and cache coherence.
• Describe parallel programming models at an introductory level.
• Describe GPU and accelerator architecture.
• Use a simulator to evaluate architectural alternatives.
• Describe power and thermal constraints on architecture.

Major Topics

Required Topics

• Computer system organisation
• Instruction set architecture
• RISC and CISC
• Addressing modes and instruction formats
• Hardware and software trade-offs
• Single-cycle datapath and control
• Multi-cycle datapath
• Pipelining
• Structural, data, and control hazards
• Forwarding, stalling, branch prediction
• The CPU performance equation
• Amdahl's law
• Memory hierarchy and locality
• Cache organisation and policies
• Average memory access time
• Virtual memory and translation
• Input/output, interrupts, DMA
• Buses and interfacing
• Computer arithmetic

Optional Topics

• Superscalar and out-of-order execution
• Multicore and cache coherence
• Parallel programming models
• GPUs and accelerators
• Architectural simulation
• Power and thermal limits

Resources & Tools

• Patterson and Hennessy, Computer Organization and Design — the standard undergraduate text worldwide; available in RISC-V, ARM, and MIPS editions, and the RISC-V edition is the current default.
• Hennessy and Patterson, Computer Architecture: A Quantitative Approach — the graduate companion; useful for depth and heavier than this course requires.
• Harris and Harris, Digital Design and Computer Architecture — if you used it for EEL3701 and EEL4712, it continues the same thread here.
• RARS or Venus — free RISC-V assembler and simulators; writing assembly is how instruction set concepts stop being abstract.
• Ripes — free; a RISC-V simulator that visualises the pipeline and cache graphically, and it is exceptionally good for understanding hazards.
• gem5 — free and open source; the research-standard architectural simulator, and heavy but real.
• Cachegrind and perf — free; measure cache behaviour on your own machine and see locality effects in real programs.
• The RISC-V specification (riscv.org) — free and open; an actual production instruction set specification you can read end to end, which is unusual and valuable.
• Godbolt Compiler Explorer — free; shows the assembly a compiler produces from source, and makes hardware/software trade-offs concrete.

Career Pathways

• Computer hardware engineers — SOC 17-2061.
• Processor and SoC design — specialised, and generally requiring graduate study.
• Performance engineering — an under-appreciated and well-paid role; understanding caches and pipelines is what makes real optimisation possible.
• Systems and embedded software engineering — this material makes a demonstrably better systems programmer, and it is common interview ground.
• Compiler engineering — code generation is architecture-driven.
• Defence and aerospace computing — L3Harris, Lockheed Martin, Northrop Grumman; embedded and radiation-tolerant computing.
• Hardware security — a growing field; speculative execution vulnerabilities are architecture problems, and understanding them requires this material.
• Accelerator and machine learning hardware — an active area with strong demand.

Special Information

⚠⚠ The asterisk in a UWF prerequisite means the course may be taken at the same time

• UWF's catalog marks a concurrent course with an asterisk, defined on the catalog's Course Information page as: "This course may be taken prior to or during the same term."
• ⚠ This is the single most useful piece of notation in the UWF engineering catalog, and it is easy to miss. A prerequisite written without an asterisk must be completed first; one written with an asterisk may be taken in the same term.
• The practical effect is on time to degree. Reading an asterisked prerequisite as a hard prerequisite adds a term to the sequence for no reason, and in a tightly chained major like electrical engineering that error compounds down the whole plan.
• Confirm with an advisor before relying on it, and note that the registration system, not the catalog text, is what actually enforces the rule.

⚠ The prerequisite is EEL4712, and it is not asterisked

• UWF publishes EEL4712 Digital Design as the sole prerequisite, which must be completed first.
• ⚠ This puts the course at the end of a four-course chain: EEL3701 → EEL4712 → EEL4713, with programming somewhere before EEL4712. A delay anywhere in that chain reaches this course directly.
• The chain also means HDL fluency is assumed — if the course includes implementation work, it will be in VHDL or SystemVerilog rather than starting from scratch.
• ⚠⚠ Plan EEL3701 in the second year if the computer engineering track matters to you; leaving it to the third makes this course a final-term risk.

⚠⚠ Performance reasoning is the course's real skill, and intuition is unreliable

• The CPU performance equation — time equals instruction count times cycles per instruction times clock period — is the framework everything hangs on. Improving one term at the expense of another is the recurring architectural trade, and clock frequency alone is a poor proxy for performance.
• ⚠⚠ Amdahl's law is the most-ignored result in the field. Speeding up a component that occupies ten percent of runtime caps total improvement at about eleven percent no matter how much faster it becomes. Measure before optimising; students and practitioners alike optimise the interesting part rather than the slow part.
• ⚠ Cache behaviour dominates real program performance more often than instruction count does. A memory access that misses to main memory costs on the order of a hundred times a cache hit, and a loop's traversal order can change its runtime by an order of magnitude without changing its instruction count at all.
• Pipelining increases throughput and increases latency. It is not a free win, and hazards impose real costs that forwarding only partly recovers.
• Branch misprediction is expensive because the pipeline must be flushed, which is why prediction accuracy matters so much in deep pipelines.

⚠ Architecture has a security dimension now

• Speculative execution vulnerabilities demonstrated that performance optimisations can leak information across security boundaries, and the affected mechanisms — speculation, caching, timing — are exactly this course's material.
• ⚠ The mitigations cost performance, which made the trade-off between speed and isolation an explicit architectural decision rather than an implicit one.
• Side channels are a general class, not a single bug: timing, power, and cache occupancy can all carry information the architecture did not intend to expose.
• This is worth understanding even for students heading into software, since the consequences appear in operating systems, browsers, and cloud isolation.

FE exam relevance

The Fundamentals of Engineering (FE) exam is the first step toward Professional Engineer licensure, and in Florida it is administered under the Florida Board of Professional Engineers. Most students take the FE Electrical and Computer exam in their final year. Licensure matters less in electrical engineering than in civil — the industrial exemption means most electrical engineers in manufacturing and product work never need a PE — but it is required for consulting practice, for sealing designs, and for power and building-systems work, which is exactly where Florida's utility and infrastructure employment sits.

Course format and position in the curriculum

• Lecture with problem sets, performance analysis, and frequently a simulator or HDL project.
• Typically taken in the fourth year, as the capstone of the computer engineering track.
• ⚠ Quantitative analysis is central. Expect to compute cache hit rates, CPI, and speedups rather than describe architectures qualitatively.
• UWF publishes no contact hours, lecture and laboratory split, or terms of offering for any course, and no material and supply fee is noted on this entry. Confirm the offering pattern with the department.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement. ⚠ For engineering specifically, ABET-accredited programmes commonly require that upper-division engineering coursework be taken in residence, so transferability of the credit and applicability to the degree are separate questions.

EEL4713 is 3 semester hours at the University of West Florida. Institutions carrying the integrated EEL4713C combine this with laboratory work in one course.