Digital Design Laboratory

Course Description

Digital Design Laboratory covers the design and applications of advanced digital logic using VHDL.

Within the SCNS taxonomy, EEL is the Electrical Engineering prefix. The University of West Florida publishes this at 1 semester hour through the Department of Electrical and Computer Engineering, College of Science and Engineering. It is offered at approximately 2 Florida institutions under this number.

⚠ This laboratory names its tool in the catalog entry, which is unusual and useful. VHDL is one of the two dominant hardware description languages, and specifying it tells a student exactly what skill they will leave with. The other is SystemVerilog, which dominates in commercial verification; the two are close enough that fluency in one makes the other a matter of weeks.

The single most important adjustment a student makes in this course is realising that VHDL is not a programming language. It looks like one, and treating it as one produces designs that simulate correctly and synthesise into something enormous, slow, or unbuildable. VHDL describes hardware that exists simultaneously; a signal assignment is a wire, not a store instruction, and a loop is replicated logic rather than an iteration in time. Students who make that shift do well and students who do not fight the tool all term.

⚠ The contact-hour figure is derived — the University of West Florida publishes none

UWF's catalog publishes a credit value in semester hours, the college and department, prerequisites, and a description. It does not publish contact hours, a lecture and laboratory split, or terms of offering for any course. It does publish a material and supply fee notice on the minority of courses that carry one — and maintains a separate Material & Supply and Equipment Fees section of the catalog — so the absence of a fee notice on this entry is meaningful, while the fee amount is not published here. Every contact-hour value in a UWF guide in this repository is therefore derived. The figure here applies the convention established for engineering and science laboratories at UWF — 45 contact hours for 1 semester hour, matching the live EVR2001L and OCE1001L rather than the 30 used for allied-health laboratories. A 1-credit engineering laboratory meeting three hours a week for a fifteen-week term reaches 45, which is the usual shape. Confirm the meeting schedule with the department.

Learning Outcomes

Required Outcomes

• Describe the design flow from HDL source through synthesis to a configured device.
• Write structurally correct VHDL entity and architecture declarations.
• Distinguish signals from variables and use each appropriately.
• Distinguish concurrent from sequential statements and their hardware meaning.
• Describe combinational logic in VHDL and avoid unintended latches.
• Describe sequential logic using clocked processes.
• Implement registers, counters, and shift registers in VHDL.
• Implement finite state machines in VHDL using a recognised coding style.
• Use standard logic types and manage type conversion correctly.
• Build hierarchical designs using component instantiation.
• Use generics and generate statements for parameterised design.
• Write a testbench and verify a design by simulation.
• Interpret simulation waveforms to diagnose design errors.
• Synthesise a design and interpret the synthesis report.
• Apply timing constraints and interpret static timing analysis results.
• Explain setup and hold time and the meaning of timing closure.
• Assign pins and configure an FPGA development board.
• Verify a design in hardware and debug discrepancies from simulation.
• Implement a design of moderate complexity to a specification.
• Document a digital design adequately for another engineer.

Optional Outcomes

• Implement a simple processor datapath and control unit.
• Interface an FPGA to external memory or peripherals.
• Apply clock domain crossing techniques correctly.
• Use on-chip logic analysis tools for hardware debugging.
• Implement a pipelined arithmetic unit.
• Compare VHDL with SystemVerilog for the same design.

Major Topics

Required Topics

• The HDL design and synthesis flow
• FPGA architecture: lookup tables, flip-flops, and routing
• VHDL entities, architectures, and ports
• Signals versus variables
• Concurrent and sequential statements
• Combinational description and inferred latches
• Clocked processes and sequential logic
• Registers, counters, shift registers
• Finite state machine coding styles
• Standard logic types and conversions
• Hierarchy and component instantiation
• Generics and generate statements
• Testbenches and simulation
• Waveform interpretation and debugging
• Synthesis reports and resource utilisation
• Timing constraints and static timing analysis
• Setup, hold, and timing closure
• Pin assignment and board configuration
• Hardware verification and debugging

Optional Topics

• Datapath and control unit design
• Memory and peripheral interfacing
• Clock domain crossing
• On-chip logic analysers
• Pipelining
• SystemVerilog comparison

Resources & Tools

• AMD Xilinx Vivado or Intel Quartus Prime — both have free editions that fully support the devices used on educational boards; whichever the department standardises on is the one to install.
• The department's FPGA development boards — Basys, Nexys, DE-series or similar; no material and supply fee is noted on this entry, unlike several other EEL laboratories.
• Chu, FPGA Prototyping by VHDL Examples — the most practical book for exactly this course, and organised around working designs.
• Ashenden, The Designer's Guide to VHDL — the thorough language reference.
• GHDL with GTKWave — free and open source; a complete VHDL simulator and waveform viewer that runs anywhere, useful for working outside the laboratory.
• EDA Playground — free browser-based HDL simulation; excellent for quick language experiments with no installation.
• Vendor coding style guides and templates — free from AMD and Intel; they document exactly which coding patterns synthesise into which hardware, which is the knowledge that separates working designs from bloated ones.
• A personal FPGA board — entry-level boards are inexpensive, and owning one removes the scheduling constraint that limits most students in this course.
• IEEE Std 1076 — the VHDL standard itself; check UWF Libraries for IEEE access.

Career Pathways

• Computer hardware engineers — SOC 17-2061.
• FPGA and digital design engineering — a persistent shortage specialism that pays well, and this course is the recognised entry point.
• ASIC design and verification — verification in particular is a large employment category, and testbench skills transfer directly.
• Defence signal processing hardware — the strongest Florida connection: radar, electronic warfare, and software-defined radio are overwhelmingly FPGA-implemented. L3Harris in Melbourne and Palm Bay, Northrop Grumman in Melbourne, Lockheed Martin in Orlando, and the programmes at Eglin Air Force Base in UWF's region.
• Aerospace and space electronics — radiation-tolerant FPGAs are standard in spacecraft, and the Space Coast sector uses them.
• High-frequency trading and low-latency systems — a niche that pays exceptionally well for FPGA skill.
• Embedded systems with programmable logic — SoC FPGAs combining processors and fabric are increasingly common.
• Test and instrumentation hardware.
• ⚠ A practical note: FPGA roles screen on demonstrable design work. Keep your projects, put them in version control, and be able to talk about a timing problem you actually fixed — that conversation is most of a junior interview.

Special Information

⚠⚠ The asterisk in a UWF prerequisite means the course may be taken at the same time

• UWF's catalog marks a concurrent course with an asterisk, defined on the catalog's Course Information page as: "This course may be taken prior to or during the same term."
• ⚠ This is the single most useful piece of notation in the UWF engineering catalog, and it is easy to miss. A prerequisite written without an asterisk must be completed first; one written with an asterisk may be taken in the same term.
• The practical effect is on time to degree. Reading an asterisked prerequisite as a hard prerequisite adds a term to the sequence for no reason, and in a tightly chained major like electrical engineering that error compounds down the whole plan.
• Confirm with an advisor before relying on it, and note that the registration system, not the catalog text, is what actually enforces the rule.

⚠⚠ A three-part prerequisite, and only the last part is concurrent

• UWF publishes: (EEL4834 OR COP3014) AND (EEL3701) AND (EEL4712*). All three conditions apply and they behave differently.
• A programming course and EEL3701 must both be completed first — neither is asterisked.
• EEL4712 is asterisked, so the Digital Design lecture may be taken prior to or during the same term — the intended pattern being lecture and laboratory together.
• ⚠ EEL3701 is the constraint that determines timing. Introductory digital systems must be complete, so plan it early if you want this laboratory in the fourth year.
• ⚠⚠ Take EEL3701L before this one where possible. It is not required, and the bench and debugging habits it builds carry directly into this course.

⚠⚠ EEL4712 lists this laboratory in return — the pair is bound together

• UWF lists EEL4712L* among the prerequisites for EEL4712, as well as listing EEL4712* here. The requirement runs in both directions.
• ⚠ The practical effect is that the pair is effectively a single unit — a student normally enrols in both in the same term, and taking the lecture without this laboratory is not the intended path.
• ⚠⚠ This is the strongest form of split-course binding in the UWF catalog, and it is the clearest evidence that the lecture and laboratory are two halves of one course. Budget for 4 semester hours total, not 3.

⚠⚠ UWF splits lecture from laboratory where many Florida institutions use one integrated C course

• UWF runs this material as a separate lecture and a separate laboratory, each with its own SCNS number and its own credit. Many other Florida institutions carry the same content in a single integrated C-suffix course.
• ⚠ The two are different SCNS numbers and SCNS equivalency does not cross numbers. A student transferring an integrated C course into UWF, or a UWF lecture-plus-lab pair out to an institution that runs the C variant, should expect the evaluation to be done by hand rather than automatically.
• Take the pair together where the department intends it. The asterisk notation described above usually permits exactly that.
• ⚠ Carry a syllabus when transferring either half. Half of an integrated course is the hardest case for a receiving evaluator to resolve from a transcript line alone.

⚠⚠ VHDL describes hardware — the mistakes all follow from forgetting that

• Everything happens at once unless you say otherwise. Concurrent statements are wires existing simultaneously, not lines executing in order, and reading an architecture top to bottom like a program is the root misconception.
• ⚠⚠ Incomplete sensitivity lists and incomplete if statements infer latches, which is the classic beginner error. A combinational process that does not assign every output on every path creates memory you did not ask for, and the design then behaves differently in hardware than in simulation. Read the synthesis warnings — the tool tells you.
• ⚠ Signals update at the end of a process; variables update immediately. Using the wrong one produces off-by-one-cycle behaviour that is maddening to trace in a waveform.
• Not everything synthesises. Delays, file I/O, and much of the language exist for simulation only, and a testbench may use constructs a synthesisable design may not.
• ⚠⚠ Division and floating point are enormous in hardware. Writing a division operator is one character and can consume a large fraction of a small device. Check the resource utilisation report rather than assuming.
• Reset strategy matters. Synchronous and asynchronous reset produce different hardware and different timing behaviour; pick one deliberately and apply it consistently.

⚠ Simulation passing is not the finish line

• A design that simulates correctly can still fail in hardware — because it does not meet timing, because a latch was inferred, or because a pin constraint is wrong.
• ⚠⚠ Timing closure is the discipline this course introduces. Static timing analysis reports whether the longest logic path fits within the clock period, and a failing path means the design does not work at that frequency no matter how correct the logic is.
• Setup and hold violations behave differently. Setup failures can be fixed by slowing the clock; hold failures cannot, and are more serious.
• ⚠ Read the reports. Synthesis and implementation produce warnings that predict most hardware failures, and students who skip them lose hours to problems the tool already identified.
• Test incrementally. Simulate each module before integrating, and get a simple design onto the board early so the toolchain and pin constraints are proven before complexity is added.
• Use version control. HDL projects accumulate generated files rapidly, and being able to return to the last working state is worth the ten minutes it takes to set up git.

Course format and position in the curriculum

• Scheduled laboratory sessions with design assignments and a substantial project.
• Taken alongside EEL4712 Digital Design, normally in the fourth year.
• ⚠ The 45-hour figure assumes a three-hour weekly session across fifteen weeks. UWF publishes no hours; confirm with the department.
• ⚠⚠ The real time commitment substantially exceeds the scheduled hours. Debugging an HDL design is not bounded by the session, and this is among the most demanding 1-credit courses in the curriculum. Budget accordingly.
• No material and supply fee is noted on this entry.

FE exam relevance

The Fundamentals of Engineering (FE) exam is the first step toward Professional Engineer licensure, and in Florida it is administered under the Florida Board of Professional Engineers. Most students take the FE Electrical and Computer exam in their final year. Licensure matters less in electrical engineering than in civil — the industrial exemption means most electrical engineers in manufacturing and product work never need a PE — but it is required for consulting practice, for sealing designs, and for power and building-systems work, which is exactly where Florida's utility and infrastructure employment sits.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement. ⚠ For engineering specifically, ABET-accredited programmes commonly require that upper-division engineering coursework be taken in residence, so transferability of the credit and applicability to the degree are separate questions.

EEL4712L is 1 semester hour at the University of West Florida. Because UWF splits this material from the lecture while many Florida institutions carry it as the integrated EEL4712C, students transferring in either direction should carry a syllabus.