Digital Design

Course Description

Digital Design covers advanced modular logic design, design languages, finite state machines, and binary logic. UWF notes that a grade of "C" or better is required in all EEL-prefixed prerequisites and a "C-" in all COP-prefixed courses.

Within the SCNS taxonomy, EEL is the Electrical Engineering prefix. The University of West Florida publishes this at 3 semester hours through the Department of Electrical and Computer Engineering, College of Science and Engineering. Institutions carrying the integrated EEL4712C offer it at approximately 3 Florida institutions.

The phrase "design languages" in the description is the whole point of the course. EEL3701 taught logic design by hand — truth tables, Karnaugh maps, state diagrams drawn on paper. That approach does not scale past a few hundred gates, and modern digital systems contain millions. A hardware description language is how the scaling problem is solved: the engineer describes behaviour and structure, and a synthesis tool produces the gate-level implementation.

⚠ The adjustment that matters is that an HDL is not a programming language. It looks like one, and treating it as one produces designs that simulate correctly and synthesise into something enormous or unbuildable. VHDL describes hardware that exists simultaneously — a signal assignment is a wire, and a loop is replicated logic rather than iteration in time. The companion laboratory, EEL4712L, is where that lesson is learned on real hardware.

⚠ Why this guide exists under this number

Many Florida institutions carry this material as a single integrated course with a C suffix. UWF instead runs a separate lecture and a separate laboratory, each with its own SCNS number, and this guide documents the UWF lecture. Its laboratory partner is documented separately in this repository. ⚠ SCNS equivalency does not cross numbers, so a transfer between the integrated and split forms is evaluated by hand rather than automatically — carry a syllabus in either direction.

⚠ The contact-hour figure is derived — the University of West Florida publishes none

UWF's catalog publishes a credit value in semester hours, the college and department, prerequisites, and a description. It does not publish contact hours, a lecture and laboratory split, or terms of offering for any course. It does publish a material and supply fee notice on the minority of courses that carry one — and maintains a separate Material & Supply and Equipment Fees section of the catalog — so the absence of a fee notice on this entry is meaningful, while the fee amount is not published here. Every contact-hour value in a UWF guide in this repository is therefore derived. The figure here applies the standard lecture convention of 15 contact hours per credit, giving 45 hours for a 3-semester-hour course. Confirm the meeting schedule with the department.

Learning Outcomes

Required Outcomes

• Describe the hardware description language design and synthesis flow.
• Describe FPGA and programmable logic device architecture.
• Write synthesisable descriptions of combinational logic.
• Write synthesisable descriptions of sequential logic.
• Distinguish constructs that synthesise from those that are simulation-only.
• Avoid unintended latch inference in combinational descriptions.
• Design hierarchical systems using modular decomposition.
• Apply parameterisation to produce reusable modules.
• Design and implement finite state machines using recognised coding styles.
• Partition a design into datapath and control.
• Design register transfer level implementations from an algorithm.
• Design arithmetic units including adders and multipliers.
• Analyse critical path and estimate maximum clock frequency.
• Apply pipelining to improve throughput and analyse its cost.
• Explain setup and hold constraints and timing closure.
• Apply clock domain crossing techniques safely.
• Write testbenches and verify designs by simulation.
• Interpret synthesis reports for resource utilisation and timing.
• Evaluate area, speed, and power trade-offs in a design.
• Document a digital design for another engineer.

Optional Outcomes

• Design a simple processor datapath and control unit.
• Describe memory interfacing and on-chip memory structures.
• Apply formal or assertion-based verification techniques.
• Describe low-power design techniques.
• Compare VHDL with SystemVerilog for the same design.
• Describe design for testability.

Major Topics

Required Topics

• HDL design and synthesis flow
• FPGA and PLD architecture
• Combinational description in HDL
• Sequential description in HDL
• Synthesisable versus simulation-only constructs
• Latch inference and how to avoid it
• Hierarchy and modular design
• Parameterised and reusable modules
• Finite state machine coding styles
• Datapath and control partitioning
• Register transfer level design
• Arithmetic units
• Critical path and maximum frequency
• Pipelining
• Setup, hold, and timing closure
• Clock domain crossing
• Testbenches and verification
• Synthesis reports and resource utilisation
• Area, speed, and power trade-offs

Optional Topics

• Simple processor design
• Memory structures and interfacing
• Assertion-based and formal verification
• Low-power design
• SystemVerilog comparison
• Design for testability

Resources & Tools

• Chu, FPGA Prototyping by VHDL Examples — the most practical book for this course, organised around working designs.
• Harris and Harris, Digital Design and Computer Architecture — carries the thread from EEL3701 through this course into EEL4713, which makes it unusually good value across three courses.
• Ashenden, The Designer's Guide to VHDL — the thorough language reference.
• AMD Xilinx Vivado or Intel Quartus Prime — free editions fully support educational boards; install whichever the department standardises on.
• GHDL with GTKWave — free and open source; a complete VHDL simulator and waveform viewer for working outside the laboratory.
• EDA Playground — free browser-based simulation; ideal for quick language experiments.
• Vendor coding style guides and inference templates — free from AMD and Intel; they document exactly which coding patterns produce which hardware, which is the knowledge that separates efficient designs from bloated ones.
• An inexpensive personal FPGA board — removes the scheduling constraint that limits most students in the companion laboratory.
• IEEE Std 1076 — the VHDL standard; check UWF Libraries for IEEE Xplore access.

Career Pathways

• Computer hardware engineers — SOC 17-2061.
• FPGA and digital design engineering — a persistent shortage specialism that pays well, and this course plus EEL4712L is the recognised entry point.
• ASIC design and verification — verification is a large employment category in its own right.
• Defence signal processing hardware — radar, electronic warfare and software-defined radio are overwhelmingly FPGA-implemented. L3Harris (Melbourne, Palm Bay), Northrop Grumman (Melbourne), Lockheed Martin (Orlando), and programmes at Eglin Air Force Base in UWF's region.
• Aerospace and space electronics — radiation-tolerant FPGAs are standard in spacecraft.
• Low-latency and high-frequency trading systems — a niche paying exceptionally well for FPGA skill.
• Embedded systems with programmable logic — SoC FPGAs combining processors and fabric.
• ⚠ FPGA roles screen on demonstrable design work. Keep your projects in version control and be ready to describe a timing problem you actually fixed.

Special Information

⚠⚠ The asterisk in a UWF prerequisite means the course may be taken at the same time

• UWF's catalog marks a concurrent course with an asterisk, defined on the catalog's Course Information page as: "This course may be taken prior to or during the same term."
• ⚠ This is the single most useful piece of notation in the UWF engineering catalog, and it is easy to miss. A prerequisite written without an asterisk must be completed first; one written with an asterisk may be taken in the same term.
• The practical effect is on time to degree. Reading an asterisked prerequisite as a hard prerequisite adds a term to the sequence for no reason, and in a tightly chained major like electrical engineering that error compounds down the whole plan.
• Confirm with an advisor before relying on it, and note that the registration system, not the catalog text, is what actually enforces the rule.

⚠⚠ EEL4712 and EEL4712L each list the other — they are bound together

• UWF lists EEL4712L* among the prerequisites for EEL4712, and lists EEL4712* as the prerequisite for EEL4712L. The requirement runs in both directions.
• ⚠ The practical effect is that the pair is effectively a single unit. Because each names the other with the concurrent asterisk, a student normally enrols in both in the same term — taking the lecture alone is not the intended path and may not be permitted.
• ⚠⚠ This is the strongest form of the split-course binding found in the UWF catalog, and it is the clearest evidence that the lecture and laboratory are two halves of one course rather than a course and an optional companion.
• Budget for both. The pair is 4 semester hours in total, not 3, and the laboratory carries its own weekly session.
• Confirm with an advisor — the registration system, not the catalog text, is what enforces this.

⚠⚠ The grade requirement differs by prefix — C for EEL, C-minus for COP

• UWF publishes a prefix-differentiated grade condition: a grade of C or better in all EEL-prefixed prerequisites and a C-minus or better in all COP-prefixed prerequisites.
• ⚠ This is a genuine trap. A student holding a C-minus in a programming course meets the requirement; the same grade in an EEL course does not. The two thresholds sit in one sentence and are easy to read past.
• ⚠⚠ UWF grade conditions are not uniform across the EEL prefix. Different courses in this same prefix require C, C-minus, or nothing at all — check each course rather than assuming a departmental standard.
• Verify against the registration system, which is what actually enforces the rule.

⚠ The full prerequisite structure

• UWF publishes: (COP2253 OR COP2334 OR COP3014 OR EEL4834) AND (EEL3701) AND (EEL4712L*).
• A programming course and EEL3701 must both be complete — neither is asterisked.
• EEL4712L is asterisked, and lists this course in return — see the reciprocal note above.
• ⚠ EEL3701 is the timing constraint. Plan it early to keep EEL4712, EEL4713 and EEL4744 available in the fourth year.
• ⚠⚠ Watch the split grade thresholds described above: C for EEL3701, C-minus for the programming course.

⚠⚠ The mistakes that follow from forgetting HDL describes hardware

• Everything happens at once unless you say otherwise. Concurrent statements are wires, not lines executing in order, and reading an architecture top to bottom like a program is the root misconception.
• ⚠⚠ Incomplete sensitivity lists and incomplete if statements infer latches. A combinational process that does not assign every output on every path creates memory you did not ask for, and the hardware then behaves differently from the simulation. Read the synthesis warnings; the tool tells you.
• ⚠ Not everything synthesises. Delays and file operations exist for simulation only, and a testbench may use constructs a synthesisable design may not.
• Division and floating point are enormous in hardware. One character of source can consume a large fraction of a device — check the utilisation report rather than assuming.
• ⚠⚠ Clock domain crossing is where subtle, intermittent failures come from. A signal sampled by an unrelated clock can go metastable, and the resulting bug appears rarely and non-reproducibly. Synchronisers exist for this and must be used deliberately.
• Reset strategy matters. Synchronous and asynchronous reset produce different hardware and different timing; choose one and apply it consistently.

⚠ Design quality is measured, not asserted

• A working design and a good design are different things, and this course is where the difference starts being graded.
• Critical path determines maximum clock frequency. Reducing it by restructuring logic or by pipelining is a core skill, and pipelining improves throughput while increasing latency and area — a trade-off, not an improvement.
• ⚠ Read the synthesis and implementation reports. Resource utilisation and timing slack are the actual feedback; students who look only at whether simulation passed miss most of what the tools are telling them.
• Verification effort exceeds design effort in practice, frequently by a large margin, and writing good testbenches is a marketable skill in itself.

FE exam relevance

The Fundamentals of Engineering (FE) exam is the first step toward Professional Engineer licensure, and in Florida it is administered under the Florida Board of Professional Engineers. Most students take the FE Electrical and Computer exam in their final year. Licensure matters less in electrical engineering than in civil — the industrial exemption means most electrical engineers in manufacturing and product work never need a PE — but it is required for consulting practice, for sealing designs, and for power and building-systems work, which is exactly where Florida's utility and infrastructure employment sits.

Course format and position in the curriculum

• Lecture with design assignments, with hardware work carried by EEL4712L.
• Typically taken in the fourth year, after EEL3701, and it is the prerequisite for EEL4713 Digital Computer Architecture.
• The real weekly commitment is for 4 credits, counting the paired laboratory, and ⚠ HDL debugging is not bounded by the scheduled session.
• UWF publishes no contact hours, lecture and laboratory split, or terms of offering for any course, and no material and supply fee is noted on this entry. Confirm the offering pattern with the department.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement. ⚠ For engineering specifically, ABET-accredited programmes commonly require that upper-division engineering coursework be taken in residence, so transferability of the credit and applicability to the degree are separate questions.

EEL4712 is 3 semester hours at the University of West Florida, taken with the 1-semester-hour EEL4712L. Institutions carrying the integrated EEL4712C cover the same material in one course.