Digital Logic and Computer Systems Laboratory

Course Description

Digital Logic and Computer Systems Laboratory covers the practical applications of digital logic. UWF notes that a material and supply fee will be assessed.

Within the SCNS taxonomy, EEL is the Electrical Engineering prefix. The University of West Florida publishes this at 1 semester hour through the Department of Electrical and Computer Engineering, College of Science and Engineering. It is offered at approximately 2 Florida institutions under this number.

⚠ The SCNS title for this number is "Introduction to Digital Systems Lab"; UWF publishes it as "Digital Logic and Computer Systems Laboratory." The local title's inclusion of computer systems suggests the laboratory reaches beyond gate-level work toward datapath and simple processor structures, which is a common late-semester progression. Confirm the scope with the instructor if it matters for planning.

Digital logic is the one area of electrical engineering where the laboratory is genuinely easier than the theory, and that inverts the usual student experience in a useful way. A logic circuit either produces the right truth table or it does not, and the failure is discrete rather than a four-percent discrepancy. The real lesson is that abstraction leaks: gates have propagation delay, outputs have limited drive, unconnected inputs float to unpredictable states, and a design that is correct in Boolean algebra can still fail on the bench because of timing. Every one of those is a preview of a problem that gets much harder at higher speeds.

⚠ The contact-hour figure is derived — the University of West Florida publishes none

UWF's catalog publishes a credit value in semester hours, the college and department, prerequisites, and a description. It does not publish contact hours, a lecture and laboratory split, or terms of offering for any course. It does publish a material and supply fee notice on the minority of courses that carry one — and maintains a separate Material & Supply and Equipment Fees section of the catalog — so the absence of a fee notice on this entry is meaningful, while the fee amount is not published here. Every contact-hour value in a UWF guide in this repository is therefore derived. The figure here applies the convention established for engineering and science laboratories at UWF — 45 contact hours for 1 semester hour, matching the live EVR2001L and OCE1001L rather than the 30 used for allied-health laboratories. A 1-credit engineering laboratory meeting three hours a week for a fifteen-week term reaches 45, which is the usual shape. Confirm the meeting schedule with the department.

Learning Outcomes

Required Outcomes

• Read a digital datasheet and identify pinout, logic levels, and timing parameters.
• Construct combinational logic circuits from a schematic.
• Verify the truth table of a constructed circuit experimentally.
• Implement Boolean functions using basic gates.
• Simplify a Boolean function and verify the simplification in hardware.
• Implement and test multiplexers, decoders, and encoders.
• Implement and test adders and comparators.
• Implement and test latches and flip-flops.
• Implement and test counters and shift registers.
• Design and test a finite state machine.
• Measure propagation delay and observe its effect.
• Identify and resolve timing hazards and glitches.
• Explain the consequences of floating inputs and apply pull-up or pull-down resistors.
• Interface logic to displays, switches, and simple output devices.
• Debug a non-functioning digital circuit systematically.
• Use a logic analyser or oscilloscope to observe digital signals.
• Keep a laboratory notebook adequate for reconstruction.
• Write a technical laboratory report.
• Apply laboratory safety and electrostatic discharge precautions.

Optional Outcomes

• Implement a design on a programmable logic device or FPGA board.
• Use a hardware description language for a simple module.
• Implement a simple datapath or arithmetic logic unit.
• Use simulation to verify a design before building it.
• Interface digital logic to a memory device.

Major Topics

Required Topics

• Digital laboratory practice and ESD precautions
• Datasheets, logic families, and logic levels
• Combinational circuit construction
• Truth table verification
• Boolean simplification in hardware
• Multiplexers, decoders, encoders
• Adders and comparators
• Latches and flip-flops
• Counters and shift registers
• Finite state machine implementation
• Propagation delay
• Hazards and glitches
• Floating inputs, pull-ups, and pull-downs
• Switch bounce and debouncing
• Displays and simple interfacing
• Systematic digital debugging
• Logic analysers and digital measurement
• Notebooks and reporting

Optional Topics

• Programmable logic and FPGA boards
• Hardware description languages
• Simple datapaths and ALUs
• Digital simulation
• Memory interfacing

Resources & Tools

• The department's bench equipment and parts — covered by the material and supply fee.
• Manufacturer datasheets (Texas Instruments, ON Semiconductor) — free; learning to read a datasheet is a course outcome and a career-long skill.
• The TI logic guide and application notes — free, and the authoritative source on logic families and level compatibility.
• Digital Design texts by Mano and Ciletti or Wakerly — whichever supports EEL3701; the theory this laboratory realises.
• Logisim Evolution — free; simulate a design before building it and the session goes far faster.
• Tinkercad Circuits — free browser-based digital simulation, useful for practising outside laboratory hours.
• A cheap logic analyser — inexpensive USB units with free software make digital timing visible, and they are worth owning.
• A personal breadboard and logic IC kit — low cost, and the fastest way to build fluency.

Career Pathways

• Computer hardware engineers — SOC 17-2061.
• Electrical and electronics engineers — SOC 17-2071 and 17-2072.
• Digital design and FPGA engineering — a well-paid specialism with persistent shortage, and this laboratory is where the path starts.
• Embedded systems and firmware engineering — a very large employment category, and hardware intuition separates a good embedded engineer from a merely adequate one.
• Hardware verification and validation.
• Florida defence electronics — L3Harris, Lockheed Martin, Northrop Grumman; radar and signal-processing hardware is FPGA-heavy work.
• Electrical and electronic engineering technicians — SOC 17-3023.
• Test engineering and manufacturing support.

Special Information

⚠⚠ The asterisk in a UWF prerequisite means the course may be taken at the same time

• UWF's catalog marks a concurrent course with an asterisk, defined on the catalog's Course Information page as: "This course may be taken prior to or during the same term."
• ⚠ This is the single most useful piece of notation in the UWF engineering catalog, and it is easy to miss. A prerequisite written without an asterisk must be completed first; one written with an asterisk may be taken in the same term.
• The practical effect is on time to degree. Reading an asterisked prerequisite as a hard prerequisite adds a term to the sequence for no reason, and in a tightly chained major like electrical engineering that error compounds down the whole plan.
• Confirm with an advisor before relying on it, and note that the registration system, not the catalog text, is what actually enforces the rule.

⚠⚠ The prerequisite is asterisked — take the lecture and this laboratory together

• UWF publishes the prerequisite as EEL3701*, so the lecture may be taken prior to or during the same term.
• Concurrent enrolment is the intended pattern and is what the split structure is built for.
• ⚠ Treating it as sequential adds a term unnecessarily.

⚠⚠ EEL3701 lists this laboratory in return — the pair is bound together

• UWF lists EEL3701L* among the prerequisites for EEL3701, as well as listing EEL3701* here. The requirement runs in both directions.
• ⚠ The practical effect is that the pair is effectively a single unit — a student normally enrols in both in the same term, and taking the lecture without this laboratory is not the intended path.
• ⚠⚠ This is the strongest form of split-course binding in the UWF catalog, and it is the clearest evidence that the lecture and laboratory are two halves of one course. Budget for 4 semester hours total, not 3.

⚠⚠ UWF splits lecture from laboratory where many Florida institutions use one integrated C course

• UWF runs this material as a separate lecture and a separate laboratory, each with its own SCNS number and its own credit. Many other Florida institutions carry the same content in a single integrated C-suffix course.
• ⚠ The two are different SCNS numbers and SCNS equivalency does not cross numbers. A student transferring an integrated C course into UWF, or a UWF lecture-plus-lab pair out to an institution that runs the C variant, should expect the evaluation to be done by hand rather than automatically.
• Take the pair together where the department intends it. The asterisk notation described above usually permits exactly that.
• ⚠ Carry a syllabus when transferring either half. Half of an integrated course is the hardest case for a receiving evaluator to resolve from a transcript line alone.

⚠ A material and supply fee is assessed for this course

• UWF publishes a fee notice on this entry but not the amount. The amount is in the catalog's separate Material & Supply and Equipment Fees section, and it is charged in addition to tuition.
• ⚠ Budget for it. Laboratory fees are billed with tuition and are not always visible when a student estimates the cost of a term from credit hours alone.
• Check whether the fee covers consumables you would otherwise buy — components, boards, and kits are frequently included, which changes the real cost comparison.

⚠⚠ Digital debugging is a method, and students who improvise flounder

• Work from the inputs forward, or from the outputs backward — but pick one and be systematic. Randomly reseating wires is the default student strategy and it is the slowest possible approach.
• ⚠ Check power and ground on every chip first. An enormous share of non-functioning digital circuits are missing one or the other on one package, and it costs ten seconds to rule out.
• ⚠⚠ Unconnected inputs are not zero. A floating CMOS input drifts, picks up noise, and produces behaviour that changes when you move your hand near the board. Tie every unused input high or low — this single rule prevents more mysterious failures than any other.
• Mechanical switches bounce for milliseconds, which a counter reads as many transitions. A counter that increments by an unpredictable amount per press is not broken; it is unbounced.
• Verify subcircuits before integrating them. Building the whole design and then testing it is how a two-hour session becomes a five-hour one.
• ⚠ Propagation delay accumulates through a chain of gates, and a circuit that is logically correct can produce transient wrong outputs. That is a hazard, not a construction error.

⚠⚠ Electrical laboratory safety is not a formality

• Benchtop supplies at the voltages used in an introductory electrical laboratory are generally not lethal, and they are entirely capable of causing burns, destroying components, and starting fires. Treat the bench as live.
• ⚠ Electrolytic capacitors fail violently when reverse-biased or over-volted, and the failure is loud, hot, and sudden. Check polarity before applying power, every time.
• ⚠⚠ Charged capacitors hold energy after the supply is switched off. Discharge them deliberately rather than assuming a powered-down circuit is a safe one.
• Current-limit the supply before energising an unfamiliar circuit. It is the single habit that prevents most component losses, and it costs nothing.
• Never work alone on an energised bench, and know where the disconnect is before you need it.
• ⚠ Eye protection matters more than students expect — component failures throw material.

⚠ Electrostatic discharge damage is real and usually invisible

• CMOS devices can be damaged by static discharge well below the threshold a person can feel.
• ⚠ The damaging outcome is the partial one. A fully destroyed chip is obvious; a partially damaged one works intermittently, and a student can lose an entire session to a device that is neither working nor visibly dead.
• Use the wrist strap and the grounded mat where the laboratory provides them, handle packages by the edges, and keep spares in conductive foam.
• When a circuit that worked stops working after handling, suspect the device before rebuilding everything else.

Course format and position in the curriculum

• Scheduled laboratory sessions with pre-laboratory preparation and written reports.
• Taken alongside EEL3701, normally in the second year.
• ⚠ The 45-hour figure assumes a three-hour weekly session across fifteen weeks. UWF publishes no hours; confirm the session length with the department.
• A material and supply fee is assessed, with the amount published separately.
• Strong preparation for EEL4712L Digital Design Laboratory, which takes the same skills to VHDL and FPGA work.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement. ⚠ For engineering specifically, ABET-accredited programmes commonly require that upper-division engineering coursework be taken in residence, so transferability of the credit and applicability to the degree are separate questions.

EEL3701L is 1 semester hour at the University of West Florida. Because UWF splits this material from the lecture while many Florida institutions carry it as the integrated EEL3701C, students transferring in either direction should carry a syllabus.