Course Description
EEE 4421C Introduction to Nanofabrication teaches how structures are built at scales below what optical inspection can resolve, and it teaches it by having students build them. The Statewide Course Numbering System description is short and unusually concrete: “This course will give the students an introduction to micro/nanofabrication tools and techniques. It includes lab sessions where the students design, fabricate and test selected micro-scale devices.”
That second sentence is the course. This is a hands-on cleanroom course, not a survey — students take a device from design through a real process sequence to measurement, which is an experience very few undergraduates get and one that employers in this field value specifically.
Two Florida institutions carry it, both at 3 credits:
- Florida International University — Introduction to Nanofabrication, matching the statewide title exactly.
- Florida Polytechnic University — Micro/Nano Fabrication and Characterization, which names the measurement half explicitly.
The two titles differ but describe the same course; Florida Poly’s simply makes the characterisation component visible in the name, and the statewide description confirms that testing is part of the sequence at both. This is title drift rather than subject divergence, and no warning is needed beyond noting it.
The statewide prerequisite is EEE 3396 (Introduction to Solid State Devices) “or with permission of the instructor.” The instructor-consent clause is worth noticing: it signals a course that admits students from adjacent programmes — materials science, mechanical engineering, physics — where the department judges the background sufficient.
Learning Outcomes
Required Outcomes
- Work safely and effectively in a cleanroom, applying gowning protocol, contamination control and chemical handling procedures.
- Explain the cleanroom classification system and why particle control determines achievable yield at micro and nano scales.
- Design a photomask layout for a simple device, accounting for alignment marks, tolerances and design rules.
- Perform photolithography — spin coating, soft bake, exposure, development — and evaluate the resulting pattern for critical dimension and edge quality.
- Explain the resolution limits of optical lithography using the Rayleigh criteria, and identify when electron-beam or nanoimprint methods are required instead.
- Select and perform an etching process, distinguishing wet from dry and isotropic from anisotropic, and evaluate selectivity and profile.
- Select and perform a thin-film deposition process — evaporation, sputtering or chemical vapour deposition — and evaluate thickness, uniformity and step coverage.
- Explain doping by diffusion and ion implantation and their role in a device sequence.
- Describe surface and bulk micromachining and the use of sacrificial layers to create freestanding structures.
- Characterise a fabricated structure using appropriate metrology: profilometry, ellipsometry, optical and electron microscopy, and four-point probe.
- Test a fabricated device electrically and relate measured performance back to specific process steps.
- Assemble individual process steps into a coherent process flow, respecting the thermal budget and step ordering.
Optional Outcomes
- Perform electron-beam lithography and evaluate its resolution and throughput trade-off.
- Apply atomic layer deposition for conformal ultra-thin films.
- Apply deep reactive ion etching for high-aspect-ratio structures.
- Describe self-assembly and bottom-up nanofabrication approaches.
- Fabricate or characterise nanomaterials: nanowires, carbon nanotubes, graphene and two-dimensional materials.
- Use atomic force microscopy and scanning tunnelling microscopy for characterisation.
- Apply microfluidic and soft-lithography fabrication techniques.
- Analyse yield, process variation and statistical process control.
Major Topics
Required Topics
- Scale and the cleanroom — the dimensional regimes from micro to nano, cleanroom classification, particle sources and contamination control, gowning, and the discipline that follows from a single particle being able to destroy a device.
- Substrates and preparation — wafer types and orientation, cleaning sequences (RCA clean, piranha), surface preparation and adhesion promotion.
- Photolithography — mask design and fabrication, positive and negative resist chemistry, spin coating and bake steps, contact, proximity and projection exposure, development, resolution and depth of focus, alignment and overlay, and lift-off as an alternative to etching.
- Advanced patterning — electron-beam lithography and the resolution/throughput trade, focused ion beam, nanoimprint lithography, and where each is the right tool.
- Etching — wet chemical etching and crystallographic (anisotropic) wet etching of silicon, plasma and reactive ion etching, deep reactive ion etching and the Bosch process, selectivity, aspect ratio, undercut and endpoint detection.
- Thin-film deposition — thermal and electron-beam evaporation, sputtering, chemical vapour deposition and its low-pressure and plasma-enhanced variants, atomic layer deposition, spin-on films, and the evaluation of conformality, stress and adhesion.
- Doping and thermal processing — diffusion and ion implantation, annealing and dopant activation, oxidation, and the thermal budget as a constraint on step ordering.
- Micromachining — bulk micromachining and anisotropic etch stops, surface micromachining with sacrificial layers, stiction and release methods, and wafer bonding.
- Metrology and characterisation — stylus and optical profilometry, ellipsometry for film thickness, optical microscopy, scanning electron microscopy, atomic force microscopy, four-point probe and electrical test structures.
- Process integration — assembling steps into a working flow, mask sequence, alignment strategy, and the design-of-experiments approach to process development.
- Device design, fabrication and test — the laboratory project: designing a micro-scale device, running it through the process, and measuring what came out.
Optional Topics
- Nanomaterials: nanowires, quantum dots, carbon nanotubes, graphene and 2D materials.
- Bottom-up fabrication and directed self-assembly.
- Scanning probe methods: AFM, STM, and probe-based lithography.
- Microfluidics, soft lithography and PDMS device fabrication.
- MEMS sensor and actuator fabrication.
- Nanophotonic and plasmonic structures.
- Packaging and encapsulation of micro-scale devices.
- Yield modelling and statistical process control.
Resources & Tools
- Introduction to Microfabrication (Sami Franssila) is the most commonly used text for a course of this shape and is written around processes rather than devices. Fundamentals of Microfabrication and Nanotechnology (Marc Madou), in three volumes, is the encyclopaedic reference for the field. Microsystem Design (Stephen Senturia) is the standard where the course leans toward MEMS.
- Silicon VLSI Technology (Plummer, Deal and Griffin) and Microchip Fabrication (Van Zant) supply the semiconductor process detail.
- Layout tools — KLayout (free), L-Edit or AutoCAD for mask design. Producing a mask layout with correct alignment marks is one of the first laboratory deliverables.
- Process simulation — the nanoHUB platform (nanohub.org, free to academic users) hosts process and device simulators; Silvaco Athena and Synopsys Sentaurus Process where TCAD is taught. CoventorWare and IntelliSuite for MEMS-specific simulation.
- Cleanroom equipment — spin coater, mask aligner, oxidation and diffusion furnaces, sputtering and evaporation systems, reactive ion etcher, wet benches, rapid thermal processor.
- Metrology equipment — profilometer, ellipsometer, optical microscope, scanning electron microscope, four-point probe, semiconductor parameter analyser.
- Facilities — FIU’s Advanced Materials Engineering Research Institute and its cleanroom; Florida Poly’s laboratories. Nationally, the NSF National Nanotechnology Coordinated Infrastructure network provides open access to university cleanrooms and runs summer programmes worth knowing about.
- Reference material — SEMI standards, the Journal of Microelectromechanical Systems, the Journal of Vacuum Science and Technology B, and the IEEE Electron Devices and Nanotechnology Councils.
Career Pathways
- Process engineer and process development engineer (SOC 17-2071, Electrical Engineers; SOC 17-2131, Materials Engineers) — the direct destination, and currently one of the strongest engineering job markets in the United States.
- MEMS design and process engineer — sensors, actuators, microphones, inertial devices and microfluidics.
- Nanofabrication engineer and cleanroom process engineer in research facilities and foundries.
- Equipment engineer at a fab or a tool vendor — Applied Materials, Lam Research, ASML, KLA, Veeco. A large employment category that students routinely overlook.
- Metrology and characterisation engineer; failure analysis engineer.
- Research technician or engineer in a university or national laboratory cleanroom — a common and accessible first job for a graduate with documented cleanroom experience.
- ⚠ The specific advantage this course confers. Very few undergraduates have hands-on cleanroom experience, and it is the single most persuasive line on a resume for process roles. Keep evidence — your process flow, your micrographs, your measured results. Employers in this field ask about specific tools you have operated, and being able to answer concretely separates candidates more than grades do.
- Florida settings include SkyWater Technology’s Kissimmee facility (advanced packaging and specialty semiconductor manufacturing in Osceola County — the most directly relevant Florida employer), L3Harris (Palm Bay, which operates its own microelectronics fabrication), onsemi, Jabil (St. Petersburg), and the university cleanrooms at FIU, USF and the University of Florida. CHIPS and Science Act investment has substantially increased demand for exactly this skill set nationally, with major fab construction in Arizona, Texas, Ohio and New York.
Special Information
⚠⚠ Cleanroom access requires separate training — arrange it in week one
This is the most actionable warning on the page. Cleanroom entry normally requires a safety course, a gowning certification and sometimes a facility-specific orientation, all arranged separately from the class. These have limited session availability and can take two or three weeks to complete.
Students who leave this to the point where the first laboratory session is scheduled lose sessions they cannot make up, because a fabrication sequence cannot be repeated on demand — furnace and deposition tools are shared, booked in advance, and process runs take days. Start the certification process the week the term begins.
⚠⚠ Chemical hazards in this course are genuinely serious
This is not a teaching laboratory where the worst outcome is a poor grade. Specific hazards, each with its own required training and procedure:
- Hydrofluoric acid, used for oxide etching, is the one that must be named explicitly. Skin contact is often painless at first, so exposure can go unnoticed while fluoride ions penetrate to bone and disrupt calcium metabolism; a modest-area exposure can be life-threatening. Calcium gluconate gel must be available, specific PPE is mandatory, and no one should handle HF without direct, specific training. If your facility’s HF procedure seems excessive, it is not.
- Piranha solution (sulphuric acid and hydrogen peroxide) is violently reactive with organics and can erupt without warning; it must never be sealed in a closed container.
- Strong bases (KOH, TMAH) used for anisotropic silicon etching are hot and caustic; TMAH is additionally acutely toxic.
- Solvents — acetone, IPA, photoresist strippers — are flammable and require fume-hood work.
- Process gases including silane (pyrophoric) and toxic dopant gases, in facilities that use them.
- High-vacuum and high-voltage equipment, RF plasma sources, and furnaces at 1000 °C and above.
Follow the facility’s standard operating procedures exactly, and never improvise a chemical step. This is also the reason the AI Integration section below carries a specific warning about generated chemical procedures.
Prerequisites
The statewide prerequisite is EEE 3396 Introduction to Solid State Devices, or permission of the instructor. What it stands for is understanding what the devices being fabricated actually are, so that a process step can be connected to a device consequence.
⚠ The unnamed requirement is chemistry. Etching, deposition, oxidation and cleaning are all chemical processes, and the course assumes working familiarity with reactions, stoichiometry and reaction kinetics. Students who deferred general chemistry will find the process material harder than classmates who did not. Reviewing reaction kinetics and the Arrhenius relation before the term is a worthwhile afternoon.
The instructor-consent route is real and worth using. Students from materials science, mechanical engineering, physics and biomedical engineering are frequently admitted, and the course serves them well — microfluidics and MEMS in particular draw from those backgrounds. If you are outside electrical engineering and want this course, ask.
⚠ Course-code variation across Florida
Micro- and nanofabrication is taught at several Florida institutions under different numbers:
- EEE 4421C — FIU and Florida Polytechnic.
- EEE 4396C Introduction to Semiconductor Manufacturing Techniques — University of Central Florida.
- EEE 4331 Microelectronic Fabrication Technologies and EEE 4420 Introduction to Nanodevices — University of Florida.
- EEE 4330 Microelectronics Engineering — Florida A&M University.
- EEE 4314C Integrated Circuit Technology — University of South Florida, which carries substantial process content.
- EEE 5427C Advanced Characterization/Fabrication — the graduate counterpart at FIU and Florida Poly.
SCNS equivalency does not cross course numbers. The content overlaps heavily across these, but a receiving programme naming its requirement by number will not match automatically. Carry the syllabus, and keep documentation of the cleanroom work — hands-on fabrication is exactly what a substitution committee and an employer both want evidenced, and a process flow with micrographs is far more persuasive than a course description.
Credit structure and the C suffix
Both institutions carry this at 3 credits as an integrated lecture-and-laboratory course. Expect the scheduled time to exceed five hours a week, and expect some of it to fall outside normal class hours: cleanroom tools are shared and booked, furnace and deposition runs take hours, and a process sequence often requires returning to the facility between scheduled sessions. Budget by contact hours and equipment availability, not by credit value.
Position in the curriculum
EEE 4421C is a senior-level elective following a devices course. At FIU it continues the sequence from EEE 3394 (electronic materials) and EEE 3396 (solid-state devices), and leads to the graduate EEE 5427C. It complements the design-oriented integrated-circuit courses by supplying the manufacturing side, and it pairs naturally with MEMS coursework (EEE 4463).
Difficulty and time commitment
The intellectual content is moderate; the logistics are what make this course demanding. Process runs are long, equipment is shared, and a mistake in week six may not be recoverable within the term. That last point is worth restating: unlike a circuits laboratory, you frequently cannot simply try again, which is an accurate rehearsal of industrial practice and is deliberately part of the pedagogy.
Plan on ten to twelve hours a week including cleanroom time, and treat scheduling as part of the work. Students who plan their tool bookings ahead complete their devices; students who do not, do not.
Articulation and transfer
SCNS records the course as guaranteed to transfer to an institution offering the same course. Two Florida institutions carry it, both at 3 credits. The course is upper-division and carries no general-education or Gordon Rule designation.
FE exam relevance
The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers semiconductor materials and devices but does not test fabrication processes. This course is taken for its own value and for its considerable employability benefit rather than for FE coverage.
AI Integration
Semiconductor and nanofabrication is an industry where machine learning is thoroughly embedded in practice and where generated advice can cause physical harm. Both belong in this section.
Where AI is genuinely used in the discipline. Modern fabs run machine learning throughout the process: defect classification from inspection imagery replaced manual review years ago; virtual metrology predicts measurements too slow to take on every wafer; predictive maintenance catches tool drift before it produces scrap; advanced process control adjusts recipes run to run; and yield analysis correlates thousands of parameters against electrical test to find root causes no engineer would find by inspection. Machine learning is also increasingly used to interpret electron microscopy and atomic force microscopy images. A graduate entering process engineering will work with these systems immediately.
Where a general-purpose assistant helps in coursework. Explaining why a Bosch-process sidewall is scalloped, or what causes stiction on release; generating scripts for process calculations and data analysis; explaining the many acronyms this field uses; helping structure a design of experiments; and drafting the process-flow documentation that laboratory reports require.
⚠⚠ Where it fails, and where the failure can injure you. Two distinct problems, and the first is a safety matter rather than an academic one.
Never take a chemical procedure from a generated answer. Models will describe HF etching, piranha preparation and solvent handling fluently and without the controls that make them survivable — omitting the PPE, the calcium gluconate provision, the container restrictions, the disposal route. The safety data sheet and your facility’s standard operating procedure are the only acceptable sources, and a generated procedure that sounds authoritative is more dangerous than no answer at all, because it invites confidence. This is the one place in this guide where the consequence of ignoring the warning is an injury rather than a grade.
⚠ The academic failure, and why it coincides with the course’s subject. The characteristic error of an AI tool asked a fabrication question is to state a recipe — a temperature, a time, a gas flow, a power, an etch rate — with confidence and without equipment context. That is precisely the misunderstanding this course exists to remove. A process recipe is not portable. It is specific to a tool, a chamber, a chamber’s recent history, a wafer size and a film stack. The same nominal recipe on two different reactive ion etchers produces different results, which is why fabs qualify each tool individually and why transferring a process between facilities is a major engineering project rather than a copy operation.
The laboratory makes this lesson concrete in a way no lecture can: you will run a documented recipe and get a different result from the documented one, and working out why is the actual content of the course. A generated recipe short-circuits that lesson by supplying a number that carries none of the conditions that determine whether it applies.
A related failure: models mix process parameters from different technology eras, blending 1990s micron-scale figures with current practice — particularly damaging in a course about how processes changed as dimensions shrank.
The engineer’s responsibility. In fabrication, a process specification is a commitment that a step will produce a stated result on a stated tool within a stated tolerance, verified by metrology. The engineer signs for the measurement, not for the plausibility of the recipe. The habit to form is to ask of every process figure: on what tool, on what stack, at what wafer size, and verified by what measurement?
Academic integrity. FIU and Florida Polytechnic each maintain academic integrity policies covering AI-generated work. Process analysis and laboratory interpretation are normally expected to be your own even where computational assistance is permitted. Generated metrology or measurement data is data fabrication — treated more seriously than plagiarism, and in a manufacturing context a direct rehearsal of professional misconduct. Ask before you rely on a tool, and disclose its use where the syllabus requires it.