EEE4376C: Introduction to Analog IC Design

Course Description

EEE 4376C Introduction to Analog IC Design is the course where analogue design moves onto silicon. On a printed circuit board a designer selects components from a catalogue with specified tolerances; on an integrated circuit the designer creates the components, and their absolute values are poor while their ratios are excellent. That single fact reorganises the whole discipline — integrated analogue design is built on matching, on differential structures and on current mirrors precisely because absolute accuracy is unavailable.

The Statewide Course Numbering System titles it Introduction to Analog IC Design and describes it as covering the “design and analysis of bipolar and MOS analog integrated circuits. Topics include operational amplifier design, analog multipliers, active loads, current sources, and active filters.” The FAMU–FSU College of Engineering gives the same description, with a prerequisite of EEE 4301.

⚠ The suffix splits this number. Florida State University carries the suffixed EEE 4376C at 3 credits. Florida A&M University carries the unsuffixed EEE 4376 under the identical title, and Florida Polytechnic University carries EEE 4376 as Analog Integrated Circuits. These are separate SCNS records; the subject is the same, the identifier is not. See Special Information.

The C suffix indicates integrated laboratory or design hours — appropriate for this subject, where the deliverable is normally a designed and simulated circuit rather than a set of solved problems.

Learning Outcomes

Required Outcomes

• Explain why integrated analogue design relies on device matching and ratios rather than on absolute component values, and identify the layout practices that achieve matching.
• Design and analyse current mirrors — simple, cascode, Widlar and Wilson — and evaluate their output resistance, compliance voltage and matching accuracy.
• Design bias networks for integrated circuits, including current references and their supply and temperature sensitivity.
• Analyse the differential pair for both bipolar and MOS implementations: transfer characteristic, differential and common-mode gain, CMRR, input range and offset.
• Analyse active loads and explain how they achieve high gain in a single stage without large passive resistors.
• Design a two-stage operational amplifier to a stated specification for gain, bandwidth, slew rate, output swing and power.
• Perform frequency compensation of a multistage amplifier, including Miller compensation with a nulling resistor, and verify gain and phase margin.
• Analyse noise in analogue integrated circuits — thermal, shot and flicker (1/f) noise — and compute input-referred noise.
• Analyse offset voltage sources, both systematic and random, and apply techniques to reduce them.
• Design analogue multipliers, including the Gilbert cell, and explain the translinear principle.
• Design active filters in integrated form, including continuous-time and switched-capacitor approaches.
• Verify a design by SPICE simulation across process, voltage and temperature corners and by Monte Carlo analysis for mismatch.

Optional Outcomes

• Design bandgap voltage references and analyse their temperature behaviour.
• Design output stages and analyse their drive capability and efficiency.
• Analyse comparators and their metastability and kickback behaviour.
• Design sample-and-hold circuits and analyse charge injection.
• Analyse fully differential amplifiers and common-mode feedback.
• Produce a physical layout for an analogue block applying matching techniques (common-centroid, interdigitation, dummy devices).
• Analyse data converter building blocks at circuit level.
• Complete a full design project from specification through schematic, simulation and layout.

Major Topics

Required Topics

• Integrated devices and matching — the components available on an integrated circuit and their tolerances; why absolute values are poor and ratios are good; random and systematic mismatch; the Pelgrom model; and the layout techniques that exploit matching.
• Current sources and mirrors — the basic mirror and its errors, cascode and low-voltage cascode mirrors, Widlar and Wilson sources, output resistance and compliance, and current-mirror-based biasing across a chip.
• Active loads — the diode-connected and current-source load, intrinsic gain g_mr_o, and why an integrated stage achieves high gain without high-value resistors.
• Differential amplifiers — the bipolar and MOS differential pair, large-signal transfer characteristic, small-signal differential and common-mode gain, CMRR and its limits, input common-mode range, and the differential pair with active load as the canonical input stage.
• Single-stage amplifier topologies in integrated form — common-source with active load, cascode and folded-cascode, telescopic structures, and the gain–swing trade-off.
• Operational amplifier design — the two-stage architecture, specification-driven design flow, systematic offset, output swing, slew rate and its relation to bias current and compensation capacitance, and power/bandwidth trade-offs.
• Frequency response and compensation — pole and zero identification in a multistage amplifier, Miller compensation and pole splitting, the right-half-plane zero and its cancellation by a nulling resistor, gain and phase margin, and settling behaviour.
• Noise — thermal noise in resistors and channels, shot noise, flicker noise and its device dependence, noise in the differential pair, input-referred noise, and the noise–power–bandwidth trade-off.
• Offset and mismatch — sources of systematic and random offset, input-referred offset, and mitigation by sizing, layout and trimming.
• Analogue multipliers — the translinear principle, the Gilbert cell, four-quadrant multiplication, and applications in mixers, modulators and variable-gain amplifiers.
• Active filters in integrated form — continuous-time g_m-C filters, switched-capacitor filters and the equivalent-resistance argument, and the tuning problem for on-chip filters.
• Simulation and verification — DC operating point, AC, transient, noise and stability analyses; process-voltage-temperature corner sweeps; and Monte Carlo analysis for mismatch.

Optional Topics

• Voltage and current references, including the bandgap reference and its curvature correction.
• Output stages: class AB in integrated form, short-circuit protection.
• Comparators, latches, kickback and metastability.
• Sample-and-hold circuits, charge injection and clock feedthrough.
• Fully differential amplifiers and common-mode feedback circuits.
• Analogue layout: common-centroid, interdigitation, dummy structures, guard rings, and substrate noise isolation.
• Data converter circuit blocks.
• A full design project taken to layout and post-layout simulation.

Resources & Tools

• Design of Analog CMOS Integrated Circuits (Behzad Razavi) is the dominant text for this course and is the book most practising analogue designers learned from. Analysis and Design of Analog Integrated Circuits (Gray, Hurst, Lewis and Meyer) is the other standard and covers bipolar design more thoroughly — relevant here, since the statewide description names bipolar and MOS explicitly. CMOS Analog Circuit Design (Allen and Holberg) is a common third adoption and is strong on the specification-driven design flow.
• The Design of CMOS Radio-Frequency Integrated Circuits (Thomas Lee) is a useful next step for students continuing toward RF.
• EDA tools — Cadence Virtuoso with Spectre is the industry standard for analogue design and is what this course will most likely use; Synopsys HSPICE and Siemens EDA tools also appear. Universities access these through Educational Alliance programmes.
• Open-source flow — Xschem, ngspice, Magic and KLayout with the SkyWater SKY130 open process design kit provide a complete and genuinely fabricable analogue flow without commercial licences.
• Process design kits — a teaching PDK at 180 nm or 130 nm is typical for analogue work. Analogue design at older nodes is not a limitation: much production analogue and mixed-signal design is still done at 180 nm and above, because the supply headroom and matching are better.
• Reference material — the IEEE Solid-State Circuits Society, the IEEE Journal of Solid-State Circuits, and the ISSCC and CICC conference digests, which are where the field’s state of the art is published.

Career Pathways

• Analog IC design engineer — the direct destination, and one of the most persistently under-supplied roles in the semiconductor industry. Analogue design has resisted automation in a way digital design has not: there is no analogue equivalent of logic synthesis, so the work remains craft-intensive and experienced designers are correspondingly scarce and well paid.
• Mixed-signal design engineer — data converters, phase-locked loops and clocking, entered from this course together with a digital IC course.
• RF integrated circuit designer — the Gilbert cell and translinear material here is the direct foundation for mixer and modulator design.
• Power management IC designer — references, regulators and converters; a large and growing employment category driven by battery-powered and automotive electronics.
• Analog verification and characterisation engineer; applications engineer at an analogue semiconductor manufacturer such as Texas Instruments or Analog Devices.
• Graduate study — analogue IC design is a field where a master’s degree is close to a standard expectation for design roles, and this course is the usual point at which a student decides to pursue one.
• Florida employers include L3Harris (Palm Bay — custom and radiation-hardened analogue and mixed-signal design, and the most direct Florida route into this career), Lockheed Martin (Orlando), Northrop Grumman (Melbourne), onsemi, and SkyWater Technology’s Kissimmee facility. ⚠ Most analogue IC design employment is outside Florida — Texas (Dallas, Austin), California, Arizona, Massachusetts and North Carolina — and a student aiming at this career should plan on a national search and should treat internships as the entry mechanism.

Special Information

⚠ The suffix problem — three institutions, two SCNS records

Number	Institution	Institutional title	Credits
EEE 4376C	Florida State University	Introduction to Analog IC Design	3
EEE 4376	Florida A&M University	Introduction to Analog IC Design	3
EEE 4376	Florida Polytechnic University	Analog Integrated Circuits	3

SCNS equivalency does not cross the suffix. Note the oddity here: FAMU and FSU share a College of Engineering and teach this course jointly, yet the statewide records show them carrying different numbers for it. A transfer evaluator matching on the exact identifier will find only one institution against EEE 4376C, which understates how widely the subject is taught.

The practical guidance is the same as for every case of this kind: carry the syllabus, present the topic list rather than the number when requesting a substitution, and raise it with an advisor in the term you transfer rather than at a final-year audit.

Prerequisites

The prerequisite at FSU is EEE 4301 Electronics II. That requirement is substantive and it is the right one: this course assumes fluent feedback analysis, including stability and compensation, from the first week. Students who passed Electronics II without genuinely understanding phase margin will struggle here, because operational amplifier design is a compensation problem — the gain is comparatively easy and the stability is the design.

⚠ A required background the prerequisite does not name. This course leans on device physics more heavily than Electronics II did: mismatch depends on device area and process, flicker noise depends on gate area and oxide quality, and the intrinsic gain g_mr_o depends on channel-length modulation. Students who took a devices course (EEE 4351, EEE 3396) find this course markedly easier. Those who did not should expect to pick up device-level reasoning as they go, and should not skip the sections of the textbook that look like revision.

Position in the curriculum

EEE 4376C is a senior-level elective in the integrated-circuit track, following Electronics II. It is one of two acceptable entry routes into EEE 4377 Mixed Signal ICs — the statewide record lists EEE 4313 or EEE 4376 as its prerequisite. Students planning to take mixed-signal design should know that whichever of the two they skip is the half they will have to acquire independently, because mixed-signal design genuinely requires both the analogue and the digital IC background.

It is also the standard preparation for graduate analogue coursework and for research in the area.

Credit structure and the C suffix

FSU carries this as an integrated course at 3 credits, so expect roughly five contact hours a week across lecture and design or laboratory sessions rather than three. Analogue design courses characteristically assess through design projects rather than examinations, and the project work expands considerably beyond scheduled hours — see the time-commitment note below.

Difficulty and time commitment

Analogue IC design is widely regarded as the hardest specialisation in electrical engineering, and this course is where students find out whether it suits them. Three specific difficulties:

• There is no unique answer. A specification can be met by several architectures with different trade-offs, and part of the assessment is justifying the choice. Students accustomed to checking against a solution key lose that support entirely.
• Every parameter trades against every other. Gain against bandwidth, noise against power, swing against gain, speed against area. Changing one to fix a failing specification breaks another, and converging on a design that meets all of them simultaneously is genuinely iterative.
• Simulation time is substantial. Corner sweeps and Monte Carlo runs take hours, so the design cycle is slow and a mistake discovered late is expensive in wall-clock time.

Plan on twelve or more hours a week in project weeks, and start assignments the day they are set. Students who begin a design project in the final week do not complete it — not because the work is long but because the iteration cannot be compressed.

The compensation is that this is a genuinely valued skill. A student who can present a designed and simulated operational amplifier with its corner and Monte Carlo results has something concrete that analogue employers understand and want.

Articulation and transfer

SCNS records the course as guaranteed to transfer to an institution offering the same course; only FSU carries this exact suffixed number. The course is upper-division and carries no general-education or Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers operational amplifiers and amplifier configurations at a level well below this course. Integrated-circuit design is not tested. This is an elective taken for its own value and for career direction rather than for FE coverage — though the op-amp material makes the corresponding FE questions straightforward.

AI Integration

Analogue IC design is the clearest case in the whole electrical engineering curriculum of a field that automation has repeatedly failed to conquer, and understanding why is genuinely instructive.

The structural fact. Digital design has logic synthesis: a designer writes behaviour in a hardware description language and a tool produces a gate-level implementation. Analogue design has no equivalent, despite forty years of attempts. Analogue circuits are sensitive to device-level effects that resist abstraction — matching, noise, parasitics, supply and substrate coupling — and the specification space is continuous and heavily coupled rather than discrete. This is precisely why analogue designers remain scarce and well paid, and it is a fact worth knowing when choosing a specialisation.

Where AI is genuinely being applied. Machine learning has made real progress on sizing — given a fixed topology, finding transistor dimensions that meet a specification — and on design-space exploration and analogue layout automation. Commercial tools now offer learned optimisation for these tasks, and research on topology generation is active. Sizing assistance is real and will be part of professional practice; topology selection and specification judgement remain human work.

Where a general-purpose assistant helps in coursework. Explaining why a folded cascode improves input common-mode range, or where the right-half-plane zero in a Miller-compensated amplifier comes from; generating SPICE decks, corner sweeps and Monte Carlo setups; writing Ocean or Python scripts for post-processing simulation results; and interpreting simulator convergence failures, which in analogue design are frequent and cryptic.

⚠ Where it fails, and why the failure is exactly what this course teaches. The characteristic error of an AI tool asked an analogue design question is to produce a topology and component values that work in an idealised setting and ignore mismatch, noise and process variation entirely. That is the precise opposite of this course’s central lesson. Integrated analogue design exists as a discipline because absolute values are unreliable and only ratios can be trusted. A generated design that specifies exact resistor values, or that assumes two transistors are identical, has ignored the one fact that makes integrated analogue design different from board-level design — and it will do so confidently, because board-level analogue dominates the training text.

A second failure follows: models report a gain or bandwidth without stating the corner and without a stability check. A design that meets its specification at the typical corner and fails at slow-slow, high-temperature, low-supply is not a design; it is a schematic. The whole verification discipline of this field is corner and Monte Carlo analysis, and it is what a generated answer omits.

The engineer’s responsibility. An analogue integrated circuit is a claim that a block will meet its specification across the process spread, the supply range and the temperature range, over the manufacturing lifetime of the part. Silicon is expensive and a respin costs months. That is why this discipline is unusually strict about evidence: the corner sweep and the Monte Carlo histogram are the design, and the schematic is only its notation. If you cannot show the worst-case corner and the mismatch distribution, you do not have a result — whatever produced the schematic.

Academic integrity. FAMU, FSU and Florida Polytechnic each maintain academic integrity policies covering AI-generated work. Design justification — the reasoning for a chosen topology and sizing — is normally expected to be your own even where scripting and simulation assistance is permitted, and it is usually the graded element in any case. Generated simulation results are data fabrication and are treated more seriously than plagiarism. Ask before you rely on a tool, and disclose its use where the syllabus requires it.