EEE4330: Microelectronics Engineering

Course Description

EEE 4330 Microelectronics Engineering is a fabrication course. Where a device course explains how a transistor behaves, this one explains how it is made — the sequence of chemical, thermal and optical processes that turn a bare silicon wafer into working integrated circuits, and the reasons each step limits what the finished device can do.

The Statewide Course Numbering System titles it Microelectronics Engineering and describes it as covering the “design and fabrication of solid-state devices. Topics include oxidation, diffusion, metallization, photolithography, and device characterization.” The FAMU–FSU College of Engineering bulletin gives the same description, with prerequisites of EEE 3300 and EEE 3300L.

⚠ One Florida institution carries this number: Florida A&M University, at 3 credits. Although the course appears in the shared FAMU–FSU College of Engineering bulletin, the statewide records show the active offering at FAMU. Students at either institution of the joint college should confirm current availability with the department, since the two share a faculty and a curriculum but not always a course inventory.

What kind of course this is. The five topics in the statewide description — oxidation, diffusion, metallisation, photolithography and characterisation — are process steps, not circuit concepts. Expect chemistry, materials science and thermodynamics alongside the electrical engineering. Students arriving from a purely circuits background regularly find the first weeks unfamiliar, and it is worth knowing that in advance rather than discovering it in week three.

Learning Outcomes

Required Outcomes

• Describe the complete process flow for a CMOS or bipolar integrated circuit and explain the purpose and ordering of each step.
• Apply the Deal–Grove model to compute oxide thickness as a function of time, temperature and ambient, and distinguish dry from wet oxidation by rate and quality.
• Calculate dopant profiles from diffusion under constant-source and limited-source conditions, applying the complementary error function and Gaussian solutions.
• Explain ion implantation, compute projected range and straggle, and account for channelling and implant damage together with the annealing required to repair it.
• Describe photolithography quantitatively: resolution and depth of focus from the Rayleigh criteria, numerical aperture, resist chemistry, exposure and development, and the alignment and overlay budget.
• Compare etching processes — wet and dry, isotropic and anisotropic — and evaluate selectivity, anisotropy and profile control.
• Describe thin-film deposition by evaporation, sputtering, and chemical vapour deposition, and select a method for a stated film requirement.
• Explain metallisation and interconnect formation, including contact and via formation, barrier layers, silicides, and the electromigration limit.
• Perform and interpret device characterisation: I–V and C–V measurement, four-point probe sheet resistance, and parameter extraction from measured data.
• Relate a process parameter to a device parameter — for example oxide thickness to threshold voltage, or implant dose to sheet resistance — and reason about the consequence of a process variation.
• Explain the sources of process variation and their effect on yield.

Optional Outcomes

• Describe crystal growth (Czochralski and float-zone) and wafer preparation.
• Describe epitaxial growth and its role in device isolation and performance.
• Describe chemical mechanical planarisation and its enabling role in multilevel metallisation.
• Analyse device scaling and the process changes it required at successive nodes.
• Describe advanced lithography: immersion, multiple patterning and extreme ultraviolet.
• Describe MEMS-specific processes including bulk and surface micromachining.
• Describe packaging, wire bonding, flip-chip and advanced packaging technologies.
• Complete a cleanroom laboratory sequence fabricating and testing a simple device.

Major Topics

Required Topics

• Silicon material and wafer preparation — crystal growth, wafer orientation and specification, defects and their consequences for yield.
• The cleanroom environment — particle classification, contamination control, why a single particle can destroy a die, and the discipline that follows from that.
• Thermal oxidation — the Deal–Grove linear–parabolic model, dry and wet oxidation, oxide quality and interface states, and the thin-oxide regime where the model breaks down.
• Diffusion — Fick’s laws, constant-source and limited-source solutions, junction depth and sheet resistance, the diffusion coefficient and its Arrhenius temperature dependence, and lateral diffusion under a mask edge.
• Ion implantation — the implanter, dose and energy, LSS range statistics, projected range and straggle, channelling, implant damage and annealing, and the advantages of implantation over diffusion for control.
• Photolithography — optical systems and numerical aperture, resolution and depth of focus, positive and negative resist, spin coating and soft bake, exposure and development, contact/proximity/projection printing, alignment and overlay, and critical dimension control.
• Etching — wet chemical etching and its isotropy, plasma and reactive ion etching, selectivity, anisotropy, aspect ratio, and endpoint detection.
• Thin-film deposition — evaporation, sputtering, atmospheric and low-pressure CVD, plasma-enhanced CVD, step coverage and conformality, and film stress.
• Metallisation and interconnect — aluminium and copper metallisation, contact resistance, silicide formation, diffusion barriers, multilevel interconnect, and electromigration as a lifetime limit.
• Process integration — assembling the steps into a complete CMOS flow; the mask sequence; isolation (LOCOS and shallow trench); the thermal budget as a global constraint.
• Device characterisation — I–V and C–V measurement, threshold voltage and mobility extraction, four-point probe, profilometry and ellipsometry, and test structures.
• Yield and variation — defect density and yield models, process control, statistical variation and its device consequences.

Optional Topics

• Epitaxy and selective epitaxial growth.
• Chemical mechanical planarisation.
• Advanced lithography: immersion, phase-shift masks, multiple patterning, EUV.
• Scaling history and the process innovations at each node; high-k dielectrics and metal gates; FinFET and gate-all-around structures.
• MEMS processes: bulk and surface micromachining, sacrificial layers, deep reactive ion etching.
• Packaging: die separation, wire bonding, flip-chip, wafer-level and advanced packaging.
• Compound semiconductor processing.
• Cleanroom laboratory: a hands-on fabrication and test sequence.

Resources & Tools

• Silicon VLSI Technology: Fundamentals, Practice and Modeling (Plummer, Deal and Griffin) is the standard reference for this course and is the most rigorous treatment of the process physics. Microchip Fabrication (Van Zant) is the most accessible and is widely used where the emphasis is practical. Fundamentals of Semiconductor Fabrication (Sze and May) and Introduction to Microelectronic Fabrication (Jaeger) are the other common adoptions, Jaeger being the most compact.
• Process simulation — Silvaco Athena and Synopsys Sentaurus Process are the industry tools; the nanoHUB platform (nanohub.org, free to academic users) hosts accessible process and device simulators that are well suited to coursework.
• MATLAB or Python for computing oxidation kinetics, diffusion profiles and implant distributions, and for plotting the resulting doping profiles. Implementing the Deal–Grove model yourself is a standard and effective exercise.
• Cleanroom facilities — where a laboratory component exists it uses a university cleanroom; typical student exercises are oxidation, photolithography patterning, etching and four-point probe measurement, often culminating in a simple MOS capacitor or resistor.
• Metrology — four-point probe, ellipsometer, profilometer, optical microscope, and a semiconductor parameter analyser.
• Reference material — SEMI standards for wafers and equipment; the International Roadmap for Devices and Systems (IRDS); the IEEE Electron Devices Society and its Transactions on Semiconductor Manufacturing.

Career Pathways

• Semiconductor process engineer (SOC 17-2071, Electrical Engineers; SOC 17-2112, Industrial Engineers for some fab roles) — the direct destination, and one of the more reliably in-demand engineering roles nationally.
• Process integration engineer — responsible for the whole flow rather than a single step; a senior route from this starting point.
• Yield enhancement engineer and failure analysis engineer.
• Equipment engineer at a fab or at a tool vendor (Applied Materials, Lam Research, ASML, KLA) — a large employment category that students frequently overlook.
• Process development engineer in MEMS, photovoltaics, display manufacturing and compound semiconductors.
• Metrology and characterisation engineer.
• ⚠ This is one of the strongest job markets in electrical engineering at present, driven by CHIPS and Science Act investment and by domestic fab construction in Arizona, Texas, Ohio and New York. Process engineering roles are numerous, well paid, and less competitive than IC design because fewer students take the fabrication path.
• Florida settings include SkyWater Technology’s Kissimmee facility in Osceola County (the former BRIDG/ICAMR centre — advanced packaging and specialty semiconductor manufacturing, and the most directly relevant Florida employer for this course), L3Harris (Palm Bay — which operates its own microelectronics fabrication for radiation-hardened devices), onsemi, Jabil (St. Petersburg), and university cleanroom facilities including USF’s Nanotechnology Research and Education Center and the FAMU–FSU College of Engineering’s own laboratories. The National High Magnetic Field Laboratory in Tallahassee also employs engineers with materials and fabrication backgrounds.

Special Information

⚠ This is a chemistry and materials course as much as an electrical one

The single most useful thing to know before registering. Oxidation is a chemical reaction whose rate is governed by diffusion through a growing film. Diffusion is Fick’s laws with an Arrhenius temperature dependence. Etching is surface chemistry. Deposition is thermodynamics and kinetics. The electrical engineering appears mainly at the end, when the finished device is characterised.

Students who chose electrical engineering partly to avoid chemistry sometimes find this course uncomfortable. Students who enjoyed chemistry and materials frequently find it the most satisfying course in the degree, because it is where the abstraction finally bottoms out in physical processes. Either way, expect to use exponentials, Arrhenius relations and error functions constantly — more than in any other course in the electrical engineering curriculum.

Prerequisites

The prerequisites are EEE 3300 and EEE 3300L — Electronics I and its laboratory. What they stand for is an understanding of what semiconductor devices are and what their parameters mean, so that a process step can be connected to a device consequence.

⚠ The unnamed requirement is general chemistry. The statewide and institutional prerequisites do not list it, but oxidation kinetics, dopant chemistry, plasma etching and deposition all assume a working knowledge of reactions, stoichiometry and thermodynamics. Most electrical engineering students will have taken CHM 2045; those who deferred it should expect to be working harder than classmates who did not. Reviewing reaction kinetics and the Arrhenius equation before the term is worthwhile and takes an afternoon.

Position in the curriculum

EEE 4330 is a senior-level elective in the microelectronics track, following Electronics I and its laboratory. It complements the device-physics courses — EEE 4351 Solid-State Electronic Devices at the same institutions — by supplying the manufacturing side of the same subject. A student taking both has a substantially more complete picture than one taking either alone, and the pair is what a fab recruiter looks for.

⚠ Course-code variation across Florida

Semiconductor fabrication is taught under several numbers in Florida, and this is one of the less portable:

• EEE 4330 — FAMU.
• EEE 4396C Introduction to Semiconductor Manufacturing Techniques — University of Central Florida: “principles, processes and equipment used in modern semiconductor fabrication; wafer processing steps, design and fabrication of semiconductor devices, complete device fabrication, industry-relevant tools, measurement techniques.” This is the closest equivalent in the state, and UCF carries it with a laboratory.
• EEE 4331 Microelectronic Fabrication Technologies — University of Florida.
• EEE 4314C Integrated Circuit Technology — University of South Florida, which carries substantial process content.
• EEE 4421C Introduction to Nanofabrication — FIU and Florida Polytechnic, at the small-scale end of the same territory.

SCNS equivalency does not cross course numbers. The content of these overlaps heavily, but a receiving programme naming its requirement by number will not match them automatically. Carry the syllabus, and where a cleanroom laboratory was involved, keep evidence of it — hands-on fabrication experience is exactly what a substitution committee and an employer both want to see documented.

Cleanroom laboratory: what to expect

Where the course includes a cleanroom component, several practical points apply:

• Access requires training. Cleanroom entry normally requires a safety course and gowning certification, arranged separately from the class. Start this in week one — students who leave it late lose laboratory sessions they cannot make up.
• The chemical hazards are real and are not like a teaching laboratory’s. Hydrofluoric acid, used for oxide etching, causes injuries that are painless at first and can be severe; piranha solution, strong bases and solvents are all in routine use. Specific training, specific personal protective equipment and specific emergency procedures apply to each. Follow them exactly.
• Furnace and implant equipment operate at high temperature and, in some cases, high voltage.
• Contamination discipline is the point, not a formality. A single skin flake or cosmetic particle can ruin a wafer and, in a shared facility, affect other users’ work.
• Process runs take days. Unlike a circuits laboratory, a fabrication sequence cannot be repeated in an afternoon — a mistake in week three may not be recoverable, which is itself an accurate rehearsal of industrial practice.

Difficulty and time commitment

The mathematics is not hard in itself — error functions, exponentials and Arrhenius relations — but the breadth is considerable, and each process step brings its own vocabulary, its own model and its own set of practical constraints. The characteristic difficulty is retention rather than derivation. Plan on eight to ten hours a week, more where a cleanroom laboratory is scheduled, and note that laboratory time is often outside normal class hours because equipment must be shared.

Articulation and transfer

SCNS records EEE 4330 as guaranteed to transfer to an institution offering the same course. Only one Florida institution carries the number, so read that guarantee narrowly and expect to argue equivalence from a syllabus. The course is upper-division, carries 3 credits, and has no general-education or Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers semiconductor materials and devices but does not test fabrication processes. This course is taken for its own value and for employability rather than for FE coverage.

AI Integration

Semiconductor manufacturing is one of the industries where machine learning has been most thoroughly and least visibly adopted, which makes this section a description of current practice rather than a caution.

Where AI is genuinely used in the discipline. Modern fabs run machine learning throughout: virtual metrology predicts a measurement that would be too slow to take on every wafer; defect classification from inspection images replaced manual review years ago; predictive maintenance anticipates tool drift before it produces scrap; advanced process control adjusts recipes run to run; and yield analysis correlates thousands of process parameters against electrical test results to find root causes no engineer would identify by inspection. A graduate entering process engineering will work with these systems immediately, and being able to interrogate them rather than merely accept their output is a genuine differentiator.

Where a general-purpose assistant helps in coursework. Explaining why the Deal–Grove model has both a linear and a parabolic regime; walking through a diffusion or implant calculation; generating MATLAB or Python code for doping profiles and oxidation kinetics; explaining an unfamiliar tool or process acronym, of which this field has an unusual number; and summarising a process flow as a starting point for checking.

⚠ Where it fails, and why the failure coincides with this course’s subject. The characteristic error of an AI tool asked a fabrication question is to state a process recipe — a temperature, a time, a dose, a gas flow — with confidence and without conditions. That is precisely the misunderstanding this course exists to remove. A process recipe is not portable. It is specific to a tool, a chamber, a wafer size, a film stack and a facility, and the same nominal recipe on two different tools produces different results. This is why fabs qualify each tool individually and why process transfer between fabs is a major engineering project rather than a copy operation. A confident recipe with no equipment context attached is not an answer, and treating it as one is the error that a process engineer is employed to prevent.

A second failure has real safety weight. Models will describe chemical procedures — HF etching, piranha preparation, solvent handling — without the controls that make them survivable. Hydrofluoric acid in particular causes injuries whose seriousness is not apparent at the time of exposure, and the correct handling procedure is a facility-specific document backed by specific training and specific antidote provision. Never take a chemical procedure from a generated answer. The safety data sheet and your facility’s standard operating procedure are the only acceptable sources, and this is the one place in this guide where the consequence of ignoring the point is physical injury rather than a poor grade.

Third: models frequently give process parameters appropriate to a technology node they have not been told about, mixing figures from 1990s micron-scale processes with current practice. Since much of this course is about how processes changed as devices scaled, an answer that blends eras is worse than no answer.

The engineer’s responsibility. In manufacturing, a process specification is a commitment that a step will produce a stated result on a stated tool within a stated tolerance, verified by measurement. The engineer signs for the measurement, not for the plausibility of the recipe. The habit worth forming here is to ask of every process figure: on what tool, on what film stack, at what wafer size, and verified by what metrology?

Academic integrity. FAMU and FSU both maintain academic honour policies covering AI-generated work. Calculations and process analysis are normally expected to be your own even where computational assistance is permitted, and generated laboratory or metrology data is data fabrication — treated more seriously than plagiarism, and in a manufacturing context a direct rehearsal of professional misconduct. Ask before you rely on a tool, and disclose its use where the syllabus requires it.