EEE4314C: Integrated Circuit Technology

Course Description

EEE 4314C Integrated Circuit Technology is carried at the University of South Florida at 3 credits. It sits at the point where device physics becomes integrated-circuit engineering: how the devices that make up an integrated circuit actually behave, how they are fabricated, and where their limitations come from.

The Statewide Course Numbering System titles the number Device Electronics for Integrated Circuits and describes it as covering “p-n junctions, bipolar transistor analysis, metal semiconductor contacts, MOS systems, MOSFET analysis and limitations,” with a statewide prerequisite of EEE 3306.

⚠⚠ Three institutions carry this number and none of them titles it the same way. This is the most tangled numbering case in the EEE prefix, and it is worth setting out before anything else:

Number	Institution	Institutional title	Credits
EEE 4314C	University of South Florida	Integrated Circuit Technology	3
EEE 4314	University of Central Florida	Device Electronics for Integrated Circuits	3
EEE 4314	Florida International University	Integrated Circuits & Systems	3
EEE 4314L	Florida International University	Integrated Circuits Laboratory	1

UCF’s title matches the statewide record exactly, and UCF’s catalog description — “p.n. junctions, bipolar transistor analysis, metal semiconductor contacts, MOS systems, MOSFET analysis and limitations” — matches it word for word. That gives a reliable anchor for what the number means at state level. USF’s Integrated Circuit Technology and FIU’s Integrated Circuits & Systems point at somewhat different emphases within the same territory. This guide covers the statewide core, which all three share, and labels the variation.

Learning Outcomes

Required Outcomes

• Analyse p-n junction electrostatics: built-in potential, depletion width, field and potential profiles, and their dependence on doping.
• Derive and apply the diode current–voltage relationship, and account for departures from ideal behaviour including recombination current and series resistance.
• Analyse junction capacitance — depletion and diffusion components — and relate it to switching speed in integrated circuits.
• Explain junction breakdown by avalanche and Zener mechanisms and the doping dependence of breakdown voltage.
• Analyse bipolar junction transistor operation from carrier transport: base transport factor, emitter injection efficiency, current gain, base-width modulation and the Early voltage.
• Analyse metal–semiconductor contacts, distinguishing rectifying Schottky junctions from ohmic contacts and explaining how ohmic contacts are engineered.
• Analyse the MOS capacitor through accumulation, depletion and inversion; interpret the C–V characteristic; and derive threshold voltage including flat-band voltage, oxide charge and body effect.
• Derive MOSFET current–voltage characteristics in triode and saturation using the gradual-channel approximation.
• Analyse MOSFET limitations: channel-length modulation, subthreshold conduction, velocity saturation, drain-induced barrier lowering, and oxide breakdown.
• Relate device structure and process parameters to circuit-level model parameters, explaining where a SPICE parameter physically comes from.
• Describe the principal integrated-circuit fabrication steps and relate each to a device characteristic.

Optional Outcomes

• Describe process integration for a complete CMOS or BiCMOS flow.
• Analyse device scaling rules and their consequences for power density and leakage.
• Describe isolation techniques, latch-up mechanisms and their prevention.
• Analyse passive components in integrated circuits: resistors, capacitors and inductors, and their tolerances and parasitics.
• Describe compound semiconductor and heterojunction devices and wide-bandgap technology.
• Perform device characterisation in the laboratory and extract model parameters from measured data.
• Use TCAD simulation to model a device structure.

Major Topics

Required Topics

• Semiconductor foundations for devices — carrier statistics, the Fermi level, drift and diffusion, generation and recombination, and the continuity equation as the tool that ties them together.
• p-n junctions — equilibrium electrostatics and the depletion approximation, band diagrams under forward and reverse bias, minority carrier injection, the ideal diode equation, non-ideal behaviour, and the ideality factor as a diagnostic.
• Junction capacitance and dynamics — depletion and diffusion capacitance, charge storage, reverse recovery, and switching-speed limits.
• Breakdown mechanisms — avalanche multiplication and Zener tunnelling, doping dependence, temperature coefficients as the practical means of telling them apart.
• Bipolar transistor analysis — structure and operating regions, minority carrier profiles in the base, current components and gain, Ebers–Moll and Gummel–Poon models, Early effect, high-injection effects, and cut-off frequency.
• Metal–semiconductor contacts — Schottky barrier formation, thermionic emission, image-force lowering, ohmic contact by heavy doping, contact resistivity, and why contacts become a limiting factor at small geometries.
• MOS systems — the MOS capacitor in accumulation, depletion and inversion; surface potential and band bending; low- and high-frequency C–V curves; flat-band voltage; fixed, mobile and interface-trapped charge; and threshold voltage derivation.
• MOSFET analysis — gradual-channel approximation, triode and saturation I–V, transconductance, output conductance, and the small-signal model derived from the physics rather than asserted.
• MOSFET limitations — channel-length modulation, subthreshold slope and its fundamental limit, velocity saturation, mobility degradation, short-channel and narrow-channel effects, hot-carrier degradation, and gate oxide reliability.
• Integrated circuit fabrication — oxidation, photolithography, etching, ion implantation and diffusion, deposition, metallisation; and how each step determines a device parameter.
• From device to model — the origin of SPICE model parameters, model levels, and what a circuit designer is implicitly assuming about the process.

Optional Topics

• CMOS and BiCMOS process integration and full process flows.
• Device scaling theory, constant-field and constant-voltage scaling, and the end of Dennard scaling.
• Isolation, latch-up and its prevention; guard rings and well contacts.
• Integrated passives: diffused and polysilicon resistors, MOS and MIM capacitors, spiral inductors and their quality factors.
• Heterojunctions, HEMTs, SiC and GaN devices.
• Non-volatile memory devices and their physics.
• Laboratory device characterisation and parameter extraction; TCAD simulation.

Resources & Tools

• Device Electronics for Integrated Circuits (Muller, Kamins and Chan) shares the statewide title and is the classic text for exactly this course — the strongest match to the statewide description. Semiconductor Physics and Devices (Neamen) and Solid State Electronic Devices (Streetman and Banerjee) are the other common adoptions; Physics of Semiconductor Devices (Sze and Ng) is the reference work for detail beyond the course.
• For the fabrication content, Silicon VLSI Technology: Fundamentals, Practice and Modeling (Plummer, Deal and Griffin) is the standard.
• Simulation — the nanoHUB tools (nanohub.org, free to academic users) provide p-n junction, MOS capacitor and MOSFET simulators that make band diagrams and carrier profiles visible under bias, which is unusually valuable for this material. Silvaco Atlas and Synopsys Sentaurus appear where TCAD is taught.
• MATLAB or Python for computing carrier concentrations, plotting band diagrams and depletion profiles, and extracting parameters from measured I–V and C–V data.
• SPICE — used here to connect physics to circuit behaviour: changing a physical model parameter and observing the terminal consequence.
• Laboratory instruments (integrated form) — semiconductor parameter analyser, C–V meter, probe station, temperature-controlled stage.
• Reference material — the Ioffe Institute semiconductor parameter database; the IEEE Electron Devices Society and the IEEE Transactions on Electron Devices; the International Roadmap for Devices and Systems (IRDS).

Career Pathways

• Device engineer and semiconductor process engineer (SOC 17-2071, Electrical Engineers) — the direct destination.
• Process integration engineer and yield engineer in semiconductor fabrication.
• TCAD and device modelling engineer; compact model engineer — the specialists who produce the SPICE models circuit designers rely on.
• Failure analysis engineer and reliability engineer — hot-carrier degradation and oxide breakdown, both covered here, are core reliability mechanisms.
• Analog and RF IC designer — designers who understand device limitations rather than only device models are measurably more effective, and this course is where that understanding comes from.
• Power electronics engineer working with SiC and GaN devices.
• Graduate study in microelectronics, nanoelectronics or photonics — this is a standard entry requirement.
• Florida settings include SkyWater Technology’s Kissimmee facility, L3Harris (Palm Bay — custom and radiation-hardened devices), onsemi, Jabil (St. Petersburg), Lockheed Martin (Orlando), and USF’s own Nanotechnology Research and Education Center, a cleanroom facility that employs undergraduates and is a genuine advantage for USF students in this field. ⚠ The largest concentrations of device and process employment remain outside Florida — Arizona, Texas, Oregon, New York and California — so plan on a national search, with CHIPS and Science Act investment gradually broadening the picture.

Special Information

⚠⚠ One number, three titles — how to tell which course you are in

As set out at the top of this guide, three institutions carry this number under three different titles, and one of them carries the suffix while the others do not. The practical guidance:

• The statewide reading is device electronics — junctions, bipolar transistors, contacts, MOS systems and MOSFET limitations. UCF’s course matches it exactly. If you need to know what the number “means” in Florida, this is the answer.
• USF’s Integrated Circuit Technology signals additional weight on fabrication and process technology — how devices are made as well as how they behave. The C suffix supports this, since process courses commonly carry laboratory or cleanroom components.
• FIU’s Integrated Circuits & Systems, with its separate EEE 4314L laboratory, signals weight on circuits built from the devices rather than on the devices alone.

A syllabus test. If the assessed work is deriving the diode equation, the threshold voltage and the MOSFET I–V relation, you are in the device-electronics reading. If it is process flows, mask sequences and cleanroom exercises, you are in the technology reading. If it is designing circuits from integrated devices, you are in the circuits-and-systems reading. Most offerings mix these; the question is where the weight falls, and the syllabus will show it in the assessment breakdown.

⚠ The suffix, and what it does to transfer

Only USF carries EEE 4314C. UCF and FIU carry the unsuffixed EEE 4314, which is a separate SCNS record, and FIU additionally carries EEE 4314L. SCNS equivalency does not cross the suffix.

Two consequences follow. A statewide inventory listing three institutions against EEE 4314C overstates the portability of that specific identifier — the honest figure is one. And a student transferring in either direction should expect to argue equivalence from a syllabus rather than from a number. Retain the syllabus and, if the course had a laboratory, a report from it.

Note also the packaging difference: FIU splits the material into a 3-credit lecture plus a 1-credit laboratory, so the FIU pair is worth 4 credits against USF’s 3, and FIU students receive two grades. Registering for the FIU lecture without the laboratory is the usual error in a split arrangement.

⚠ Do not confuse this with the neighbouring numbers

Several nearby numbers carry closely related but distinct subjects, and confusing them is easy:

• EEE 4310 — VLSI Circuit Design (UF, UWF): designing digital circuits from devices, rather than analysing the devices.
• EEE 4313 — CMOS Digital IC Design (FAMU, FSU): the same territory as EEE 4310.
• EEE 4351 / EEE 4351C — Solid-State Electronic Devices / Semiconductor Devices: overlapping device-physics content at FAMU, FSU and USF. USF carries both EEE 4314C and EEE 4351C, so at USF these are genuinely two different courses and the distinction matters when planning.
• EEE 4330 — Microelectronics Engineering (FAMU): the fabrication half treated as its own course.

Prerequisites

The statewide prerequisite is EEE 3306. Institutional requirements differ and are what bind — check your own catalog. UCF requires EEE 3350 Semiconductor Devices for its version of the number.

What the prerequisite stands for is a first course in semiconductor devices or electronics. ⚠ The unnamed requirement is mathematical maturity of a particular kind: this course integrates across a depletion region, solves the continuity equation with boundary conditions, and reasons about exponential carrier profiles. It is calculus applied to physical distributions rather than algebra applied to circuits, and students who found circuits comfortable because the mathematics was procedural sometimes find this course a step change. Comfort with exponentials and with setting up a boundary-value problem is the practical requirement.

Position in the curriculum

EEE 4314C is a senior-level course in the microelectronics track. It follows a first devices or electronics course and precedes work in integrated circuit design, fabrication and nanotechnology. At USF it sits alongside EEE 4351C Semiconductor Devices and supports the graduate sequence (EEE 5356C, EEE 6353, EEE 6358, EEE 6397), which USF carries in unusual depth — a signal that this is a genuine research strength there.

Difficulty and time commitment

This is a demanding course whose difficulty lies in the length of its derivations. The MOSFET threshold voltage and the bipolar current gain each take pages, and a student who memorises endpoints without following the argument cannot adapt them — which is exactly what examinations require. Plan on nine to eleven hours a week.

The single highest-value skill is drawing energy band diagrams under bias. Most questions in this subject can be answered from a correct band diagram, and most wrong answers begin with an incorrect one. Practise them until they are automatic.

Articulation and transfer

SCNS records this course as guaranteed to transfer to an institution offering the same course; as set out above, only USF offers this exact number. The course is upper-division, carries 3 credits, and has no general-education or Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers semiconductor materials and devices within its Electronics topic area — band gaps, doping, carrier transport, junction behaviour and transistor operation. This course treats that material considerably more deeply than the exam requires, which makes it comfortable preparation. The FE tests application rather than derivation, so a targeted review of the summary relationships is still worthwhile.

AI Integration

Device physics is an area where AI assistance is genuinely useful for explanation and consistently unreliable for values, and this course is a good place to learn the difference.

Where AI is used in the discipline. Machine learning has become a real tool in semiconductor process control — yield prediction, defect classification from inspection images, and virtual metrology are all in production use in fabs. Compact model parameter extraction, historically a laborious fitting exercise, increasingly uses learned optimisation. A student entering process or device engineering will meet these systems, and understanding what they are fitting is part of the job.

Where a general-purpose assistant helps in coursework. Explaining why the depletion region widens under reverse bias or what inversion physically means, in different words from the textbook; walking through the algebra of a long derivation; generating plotting scripts for band diagrams, carrier profiles and C–V curves; and explaining the physical meaning of an unfamiliar SPICE model parameter.

⚠ Where it fails, and why the failure is exactly this course’s subject. The characteristic error is that a model supplies a device parameter without the conditions that define it — a threshold voltage, a mobility, a saturation current — when the entire content of this course is that these are functions, not constants. Threshold voltage depends on oxide thickness, substrate doping, and body bias. Mobility depends on doping, temperature and field. Saturation current depends exponentially on temperature. A confident number with no conditions attached is precisely the misconception the course exists to remove.

A second failure is more damaging still: models reliably apply the long-channel square-law MOSFET model to short-channel devices, producing current predictions wrong by large factors. That is not a subtle slip — “MOSFET analysis and limitations” is in the statewide description, and short-channel behaviour is the limitation. The square law dominates the training text, so a generated answer sails past the very point of the second half of the course.

Third, models produce band diagrams that are qualitatively wrong — bending the wrong way under bias, or misplacing the Fermi level in a doped or biased region. Since the band diagram is the reasoning tool of the whole subject, an incorrect one propagates into every conclusion drawn from it.

The engineer’s responsibility. A device parameter used in a design is a claim about behaviour under stated conditions of temperature, bias and process, and the engineer signs for the conditions as much as for the number. The habit to form here is to ask of every value: at what temperature, at what doping, at what bias, at what channel length, and measured how? A foundry model card or a parameter database answers those questions; a generated number generally does not. Draw the band diagram yourself — it is the cheapest reliable check this subject offers.

Academic integrity. USF, UCF and FIU each maintain academic integrity policies covering AI-generated work, and practice varies by instructor. Derivations are normally expected to be your own even where computational and plotting assistance is permitted. Where the course includes laboratory characterisation, generated measurement data is data fabrication and is treated more seriously than plagiarism. Ask before you rely on a tool, and disclose its use where the syllabus requires it.