EEE4313: CMOS Digital IC Design

Course Description

EEE 4313 CMOS Digital IC Design is the undergraduate introduction to designing digital integrated circuits at the transistor level. It sits deliberately between two courses a student has already taken: device physics explains what a MOSFET does, digital logic explains what a gate should do, and this course is where those meet — building the gate out of transistors, sizing it, laying it out, and accounting for the delay and power that result.

The Statewide Course Numbering System titles the number Introduction to Digital Integrated Circuit Design and lists its content precisely: “semiconductor device physics, digital logic fundamentals, static inverter analysis, static logic gate analysis, dynamic switching analysis, combinational logic design.” That sequence is the course’s actual structure — it begins with the device, establishes the inverter as the canonical case, generalises to gates, then adds timing.

Two Florida institutions carry it, both at 3 credits and both under the identical title CMOS Digital IC Design: Florida A&M University and Florida State University, sharing the joint FAMU–FSU College of Engineering. FSU describes it as introducing “students to the design of CMOS digital IC circuits using IC layout techniques” — the mention of layout is significant, because it means the course goes beyond schematic-level analysis to the physical realisation.

The two institutions agree exactly on title, credits and description, so this guide can be definite about content. What differs is the route in, and that turns out to matter.

Learning Outcomes

Required Outcomes

• Apply MOSFET device models — threshold voltage, triode and saturation behaviour, body effect and channel-length modulation — at the level of detail digital design requires.
• Derive the static CMOS inverter voltage transfer characteristic and determine the switching threshold as a function of transistor sizing.
• Determine noise margins from the transfer characteristic and explain what a noise margin guarantees in a real system.
• Analyse dynamic switching behaviour: charging and discharging of load capacitance, propagation delay, rise and fall times, and the RC delay model.
• Compute the components of power dissipation — dynamic switching power, short-circuit power and leakage — and evaluate the power–delay and energy–delay products.
• Size transistors for balanced rise and fall times and for a target delay, applying logical effort or an equivalent method.
• Design static CMOS combinational gates from a Boolean specification by constructing complementary pull-up and pull-down networks.
• Analyse the effect of fan-in and fan-out on delay, and design buffer chains for large loads.
• Produce a physical layout for a gate satisfying a given design-rule set, and explain what each rule protects against.
• Identify parasitic capacitance and resistance arising from a layout and account for their effect on delay.
• Verify a design by SPICE simulation and reconcile hand calculation with simulated result.

Optional Outcomes

• Analyse sequential elements — latches and flip-flops — at transistor level, including setup, hold and clock-to-Q timing.
• Analyse dynamic, domino and pass-transistor logic families and compare them against static CMOS.
• Analyse memory cells: SRAM read and write stability, DRAM operation and sense amplification.
• Design arithmetic building blocks such as adders and multipliers at transistor level.
• Apply low-power techniques including voltage scaling, clock gating and multi-threshold CMOS.
• Write and simulate hardware description language for a standard-cell flow, and contrast it with full-custom design.
• Analyse interconnect delay, crosstalk and signal integrity.

Major Topics

Required Topics

• Semiconductor device physics for digital design — the MOS structure, threshold voltage and its dependencies, the square-law model, velocity saturation and short-channel effects, subthreshold conduction, and the device capacitances that determine switching speed.
• Digital logic fundamentals in a circuit context — logic levels as voltage ranges, the digital abstraction and the conditions under which it holds, restoring logic, and regenerative behaviour.
• Static inverter analysis — the voltage transfer characteristic region by region, switching threshold, the beta ratio and its effect, V_IL, V_IH, V_OL, V_OH and the derivation of noise margins.
• Static logic gate analysis — complementary pull-up and pull-down networks, series and parallel transistor stacks, equivalent width calculation, NAND versus NOR asymmetry, and complex gate construction.
• Dynamic switching analysis — load capacitance components, the RC delay model, propagation delay and transition times, the delay penalty of stacking, and Elmore delay for chains.
• Power dissipation — dynamic power and the CV²f relation, activity factor, short-circuit current and its dependence on input slope, subthreshold and gate leakage, and the trade-offs against supply voltage.
• Transistor sizing — sizing for symmetric transitions, logical effort and electrical effort, optimal fan-out in a buffer chain, and the diminishing returns of upsizing.
• Combinational logic design — from Boolean expression to transistor topology, gate-level optimisation for delay rather than for gate count, and the difference between minimising literals and minimising delay.
• IC layout techniques — stick diagrams, design rules and their manufacturing rationale, the Euler-path method for compact layout, well and substrate contacts, and latch-up prevention.
• Parasitics — diffusion and interconnect capacitance, wire resistance, extraction from layout, and the difference between pre-layout and post-layout timing.
• Simulation and verification — SPICE transient and DC transfer analysis, design-rule checking and layout-versus-schematic verification.

Optional Topics

• Sequential circuit design: latches, flip-flops, clocking disciplines, setup and hold analysis, metastability.
• Dynamic, domino and pass-transistor logic families.
• Memory design: SRAM cell stability, DRAM, decoders and sense amplifiers.
• Datapath elements: adders, multipliers, shifters.
• Low-power design techniques.
• Interconnect, crosstalk and signal integrity.
• Standard-cell and synthesis-based flows; design for testability.

Resources & Tools

• Digital Integrated Circuits: A Design Perspective (Rabaey, Chandrakasan and Nikolic) is the standard text for this course and matches its structure closely, particularly the inverter-first development. CMOS VLSI Design: A Circuits and Systems Perspective (Weste and Harris) is the other common adoption and is the source of the logical-effort treatment. CMOS Digital Integrated Circuits: Analysis and Design (Kang and Leblebici) is frequently used where the emphasis is on analysis.
• SPICE — HSPICE, Spectre, LTspice or ngspice. The two workhorse analyses here are DC transfer (for the inverter characteristic and noise margins) and transient (for delay and power).
• Layout and verification tools — Cadence Virtuoso with Assura or PVS for DRC and LVS is the industry standard; Synopsys and Siemens EDA Calibre also appear. Universities access these through Educational Alliance programmes.
• Open-source flow — Magic, KLayout, Xschem and ngspice with the SkyWater SKY130 open process design kit now make a complete and genuinely fabricable design flow available without commercial licences; several universities have moved coursework onto it.
• Process design kits — teaching PDKs at 180 nm, 130 nm or 45 nm are typical. The node matters: short-channel effects and leakage behave very differently across them, and a result derived at one node does not transfer to another.
• Reference material — the IEEE Solid-State Circuits Society, the IEEE Journal of Solid-State Circuits, the ISSCC digest, and the International Roadmap for Devices and Systems (IRDS).

Career Pathways

• Digital IC design engineer and VLSI design engineer (SOC 17-2061, Computer Hardware Engineers) — the direct destination.
• Physical design engineer — place-and-route, timing closure and signoff; a large specialisation that the layout and parasitics material introduces.
• Standard cell library engineer — a niche that this course maps onto almost exactly, since a standard cell is a hand-designed, characterised CMOS gate.
• Static timing analysis engineer and design verification engineer.
• Low-power design engineer — increasingly central as mobile and edge devices dominate volume.
• Computer hardware engineer (SOC 17-2061) and electronics engineer (SOC 17-2072) more broadly.
• Florida employers include L3Harris (Palm Bay — custom and radiation-hardened integrated circuits, and the most likely Florida route into IC design), Lockheed Martin (Orlando), Northrop Grumman (Melbourne), SkyWater Technology’s Kissimmee facility, onsemi and Jabil in Tampa Bay. ⚠ Most digital IC design employment is outside Florida — California, Texas, Oregon, Arizona and Massachusetts — and a student planning this career should expect a national job search and should treat internships as the entry mechanism. CHIPS and Science Act investment is gradually improving the domestic picture, including in Florida.

Special Information

⚠ Two different entry routes, and the class arrives unequal

FSU sets different prerequisites depending on major:

• Electrical engineering majors: EEE 3300 (Electronics I) — a device-and-circuits background.
• Computer engineering majors: EEL 3003 — a general electrical engineering course.

This is a sensible administrative accommodation, but it has a real consequence: the two groups arrive with materially different preparation in MOS device behaviour. A student entering through EEE 3300 has already derived MOSFET characteristics and worked with small-signal and large-signal models. A student entering through EEL 3003 generally has not.

If you are entering by the computer engineering route, expect the opening weeks — the semiconductor device physics the statewide description lists first — to be new material rather than revision, and plan accordingly. The device content is not deep, but it is assumed quickly, and falling behind in the first fortnight is the common failure pattern in this course.

⚠ Course-code variation across Florida

Digital IC and VLSI design is taught at most Florida engineering programmes under different numbers:

• EEE 4313 — FAMU and FSU.
• EEE 4310 — University of Florida (VLSI Circuits and Technology 1) and University of West Florida (VLSI Circuit Design).
• EEE 4334 — University of Central Florida (Introduction to VLSI Design), which requires both EEE 3342C and EEE 3307C with a C or better.
• Graduate-level treatments appear as EEE 5315, EEE 5327 and EEE 6323.

SCNS equivalency does not cross course numbers. The content corresponds closely across these four, but a receiving programme naming its prerequisite by number will not match them automatically. Carry the syllabus and a graded layout assignment, and request the substitution early rather than in a final-year audit.

Position in the curriculum

EEE 4313 is a senior-level elective, and at the FAMU–FSU College of Engineering it is a gateway into the integrated-circuit track. It supports EEE 4377 Mixed Signal ICs, for which the statewide record lists EEE 4313 or EEE 4376 as the entry, and it is the natural precursor to graduate work in EEE 5315 Digital Integrated Circuit Design.

Because EEE 4377 accepts either this course or the analogue IC course as its prerequisite, students planning to take mixed-signal design should be aware that whichever of the two they skip is the half they will have to pick up later — mixed-signal design genuinely needs both.

Difficulty and time commitment

The analysis is more tractable than in an analogue course — digital circuits are switching between two states rather than operating in a linearised region, and much of the work is algebraic. The time goes into the tools. A first layout that passes design-rule checking and layout-versus-schematic verification takes far longer than the design it represents, and the failure mode is a long tail of small violations rather than one large problem. Plan on nine to eleven hours a week, weighted toward tool work, and start layout assignments early.

The compensating advantage is that this tool fluency is directly marketable, and employers know what it costs to acquire. A student who can describe a full-custom cell taken through DRC, LVS and post-layout simulation has something concrete and credible to discuss in an interview.

Articulation and transfer

SCNS records EEE 4313 as guaranteed to transfer to an institution offering the same course — here, the two institutions of the joint college. Both carry it at 3 credits. The course is upper-division and carries no general-education or Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers digital systems and electronics, including semiconductor devices and logic fundamentals, but does not test integrated-circuit design or layout. This course supports the relevant FE topics indirectly and should not be treated as focused FE preparation.

AI Integration

Digital IC design is a field where machine learning has been genuinely adopted in the professional tool flow, which makes this more than a warning section.

Where AI is genuinely used in the discipline. Commercial EDA vendors ship reinforcement-learning-based placement and routing (Synopsys DSO.ai, Cadence Cerebrus), and learned optimisation now appears in timing closure, cell sizing and design-space exploration in production flows. Machine learning is also used in fabrication for yield prediction and defect classification. A graduate entering this field will use AI-assisted tools professionally — which is a reason to understand what they optimise, not a reason to avoid them.

Where a general-purpose assistant helps in coursework. Explaining logical effort or walking through a noise-margin derivation in different words; generating SPICE decks and parameter sweeps; writing Tcl or SKILL automation scripts; and interpreting the notoriously cryptic DRC and LVS error messages, which is a genuine and substantial time saving for a beginner.

⚠ Where it fails, and why the failure is precisely this course’s subject. The characteristic error of an AI tool asked a digital IC question is to answer using the digital abstraction — the very abstraction this course exists to take apart. Asked about a CMOS NAND gate, it will explain the truth table. But the question in this course is never the truth table: it is what the output voltage actually reaches, how long the transition takes at a given fan-out, how much charge it costs, and whether the noise margin survives. A generated answer that is correct at the logic level is useless at the circuit level, and it is confidently correct in a way that masks the fact that it has not addressed the question.

Two concrete failures follow. Models routinely quote propagation delay, threshold voltage and power figures with no process, supply voltage, temperature or load attached — numbers that sound authoritative and mean nothing without those conditions, when the entire discipline of a technology-aware design course is that circuit behaviour is a property of the process it is built in. And they consistently underweight parasitics, giving pre-layout answers to post-layout questions — which is the single most common way a student design passes simulation and fails in silicon.

A third, specific to layout: models will produce design rules that correspond to no real PDK, mixing lambda-based teaching rules with micron-based foundry rules. A layout built on those rules will not pass DRC against any actual process.

The engineer’s responsibility. In integrated-circuit design the verification chain is the deliverable: DRC, LVS, and post-layout simulation with extracted parasitics, against a specific process at stated conditions. A design is not correct because it looks correct or because a tool proposed it. Tape-out is expensive and irreversible, which is why this discipline is stricter than most about what counts as evidence.

Academic integrity. FAMU and FSU both maintain academic honour policies covering AI-generated work. Layout and design assignments are normally expected to be individual work even where scripting assistance is permitted, and submitting a layout you did not construct is straightforwardly a violation. Ask your instructor what is allowed before relying on a tool, and disclose its use where the syllabus requires it.