EEE4310: VLSI Circuit Design

Course Description

EEE 4310 VLSI Circuit Design is the undergraduate introduction to very-large-scale integrated circuit design — the point at which a student stops designing with components and starts designing the components themselves, laying out transistors on silicon and reasoning about what the manufacturing process will actually produce.

The Statewide Course Numbering System titles the number Digital Integrated Circuits and describes it as covering “the analysis and design of digital circuits that are fabricated using MOS and bipolar devices.” Two Florida institutions carry it, both at 3 credits:

• University of West Florida — VLSI Circuit Design: “analysis and design of digital circuits using MOS and bipolar devices,” which follows the statewide description almost word for word.
• University of Florida — VLSI Circuits and Technology 1: “introduction to VLSI circuit technology and manufacturing; fabrication, device models, layout, parasitics, and simple gate circuits.”

⚠ The two are the same subject with a different centre of gravity. UWF’s version leads with circuit analysis and design; UF’s leads with technology and manufacturing — fabrication steps, device models derived from process parameters, physical layout and parasitic extraction. A student who wants to design logic will find both useful; a student who wants to understand why a design behaves differently in silicon than in simulation will find UF’s framing more directly aimed at that. The distinction is one of emphasis, not of subject, and this guide covers both with the variation labelled.

UF’s “1” in the title signals a sequence: UF continues into EEE 6323 VLSI Circuits and Technology 2 at graduate level. UWF carries a graduate counterpart at EEE 5327 VLSI Circuit Design, described as advanced topics in the same area with additional study of layout and CAD tools.

Learning Outcomes

Required Outcomes

• Describe the principal steps of CMOS fabrication — oxidation, photolithography, etching, ion implantation, diffusion, deposition and metallisation — and relate each to a feature of the finished device.
• Interpret and apply MOS device models, including threshold voltage, the square-law and short-channel behaviour, body effect and channel-length modulation, as they appear in circuit design.
• Derive the CMOS inverter voltage transfer characteristic and determine switching threshold, noise margins and the effect of transistor sizing.
• Calculate propagation delay, rise and fall times, and the effect of load capacitance and fan-out; apply logical effort or an equivalent sizing method.
• Analyse power dissipation in CMOS — dynamic switching, short-circuit and leakage components — and evaluate the power–delay and energy–delay products.
• Design static CMOS combinational gates from a Boolean specification, constructing complementary pull-up and pull-down networks and sizing for balanced drive.
• Produce a physical layout for a simple gate that satisfies a given set of design rules, and explain the purpose of each rule in terms of manufacturing tolerance.
• Identify parasitic resistance and capacitance from a layout and explain their effect on delay and on signal integrity.
• Analyse sequential elements — latches and flip-flops — at the transistor level, including setup, hold and clock-to-Q timing and their circuit origins.
• Use industry-standard EDA tools to schedule a design through schematic capture, simulation, layout, design-rule checking and layout-versus-schematic verification.

Optional Outcomes

• Design and analyse dynamic, domino and pass-transistor logic families and compare them against static CMOS.
• Analyse memory arrays — SRAM and DRAM cells, decoders and sense amplifiers.
• Design arithmetic building blocks (adders, multipliers) at transistor level and evaluate architectural trade-offs.
• Analyse clock distribution, skew and jitter.
• Apply low-power design techniques such as voltage scaling, clock gating and multi-threshold CMOS.
• Write and synthesise hardware description language for a standard-cell flow, and contrast it with full-custom design.
• Analyse bipolar and BiCMOS digital circuits (named explicitly in the statewide and UWF descriptions).

Major Topics

Required Topics

• CMOS process technology — wafer preparation, oxidation, photolithography and masking, etching, doping by diffusion and ion implantation, thin-film deposition, metallisation and planarisation; the n-well, p-well and twin-well processes.
• MOS device models for design — threshold voltage and its dependencies, the long-channel square law, velocity saturation and short-channel effects, subthreshold conduction, and the SPICE model levels used in practice.
• The CMOS inverter — voltage transfer characteristic, switching threshold, noise margins, the ratio of pull-up to pull-down strength, and the beta ratio.
• Delay and drive — RC delay models, propagation delay, fan-out and load, buffer chains, and logical effort as a sizing discipline.
• Power — dynamic power and the CV²f relationship, short-circuit current, leakage and its growing dominance at small geometries, and the energy–delay trade-off.
• Combinational CMOS design — complementary networks, complex gates, transmission gates, and the translation from Boolean expression to transistor topology.
• Layout and design rules — stick diagrams, lambda- and micron-based rules, the Euler-path method for efficient layout, well and substrate contacts, and latch-up prevention.
• Parasitics and interconnect — wire resistance and capacitance, RC interconnect delay, coupling and crosstalk, and electromigration as a reliability limit.
• Sequential elements — latches and flip-flops at transistor level, master–slave structures, clocking disciplines, setup and hold time, and metastability.
• The design flow and verification — schematic capture, SPICE simulation, layout, design-rule checking (DRC), layout-versus-schematic (LVS) and parasitic extraction.

Optional Topics

• Dynamic, domino, NORA and pass-transistor logic families.
• Memory design — SRAM and DRAM cells, arrays, decoders, sense amplifiers and read/write margins.
• Datapath elements — ripple-carry, carry-lookahead and carry-select adders; array and Wallace-tree multipliers.
• Clock distribution, H-trees, skew and jitter budgets.
• Low-power design: voltage and frequency scaling, clock gating, power gating, multi-Vt.
• Standard-cell and semi-custom flows; synthesis from HDL; place and route.
• Yield, process variation and statistical design; testing and design for testability.
• Bipolar and BiCMOS digital circuits.

Resources & Tools

• CMOS VLSI Design: A Circuits and Systems Perspective (Weste and Harris) is the dominant text for this course and the source of the logical-effort treatment. Digital Integrated Circuits: A Design Perspective (Rabaey, Chandrakasan and Nikolic) is the other standard adoption and is stronger on device physics and power; CMOS Digital Integrated Circuits (Kang and Leblebici) is also common. For the fabrication material in UF’s version, Silicon VLSI Technology (Plummer, Deal and Griffin) is the reference.
• EDA tools — Cadence Virtuoso (schematic, layout, Spectre simulation, Assura or PVS for DRC/LVS) is the industry standard and is used at UF; Synopsys and Siemens EDA (Mentor) Calibre also appear. Universities access these through the Educational Alliance programmes, which is worth knowing because the tools are otherwise prohibitively expensive.
• Open-source alternatives — Magic, KLayout, Xschem and ngspice, together with the SkyWater SKY130 open process design kit, now make a complete design flow available outside a licensed laboratory. Several universities use these for coursework, and the SKY130 PDK is genuinely fabricable through multi-project wafer shuttles.
• Process design kits — teaching PDKs at 180 nm, 130 nm or 45 nm are typical; the specific node matters because short-channel effects dominate differently at each.
• Reference bodies and material — the IEEE Solid-State Circuits Society, the IEEE Journal of Solid-State Circuits, the International Solid-State Circuits Conference (ISSCC) digest, and the International Roadmap for Devices and Systems (IRDS), which replaced the ITRS and is the standard reference for where the technology is going.

Career Pathways

• VLSI design engineer and digital IC design engineer (SOC 17-2061, Computer Hardware Engineers) — the direct destination.
• Physical design engineer — place-and-route, timing closure and signoff; a large and well-paid specialisation that this course’s layout and parasitics material introduces.
• Design verification engineer; DFT (design-for-test) engineer; static timing analysis engineer.
• Process integration engineer and yield engineer in semiconductor manufacturing — the route UF’s technology-and-manufacturing emphasis points at most directly.
• Analog/mixed-signal IC designer, for students who combine this with the analogue IC sequence.
• Hardware security engineer — UF is a national centre in this area, and its hardware security and physical-inspection courses (EEE 4714, EEE 4740) build directly on VLSI understanding.
• ⚠ A note on the Florida job market. Semiconductor design is concentrated in California, Texas, Oregon, Arizona and Massachusetts, and most graduates entering pure IC design relocate. Florida-based opportunities do exist — L3Harris (Palm Bay, radiation-hardened and custom devices), Lockheed Martin (Orlando), Northrop Grumman (Melbourne), SkyWater Technology’s Kissimmee facility (the former BRIDG/ICAMR centre in Osceola County, which does advanced packaging and specialty semiconductor work), and onsemi and Jabil in the Tampa Bay area — and CHIPS and Science Act investment has increased activity. But a student planning a VLSI career should plan on a national job search, and should treat internships as the mechanism for entering it.

Special Information

⚠ Institutional variation: circuits versus technology

Both institutions teach VLSI design; they weight it differently, and a student choosing or transferring should know which:

UWF — VLSI Circuit Design	UF — VLSI Circuits and Technology 1
Analysis and design of digital circuits	VLSI circuit technology and manufacturing
MOS and bipolar devices named explicitly	Fabrication steps and process flow
Circuit-first framing	Device models derived from process parameters
Continues to EEE 5327 (graduate), adding layout and CAD tools	Layout, parasitics and simple gate circuits; continues to EEE 6323

A syllabus test: if the assessed work is inverter sizing, logical effort and gate-level delay calculation, it is the circuits framing; if it includes process cross-sections, mask sequences and parasitic extraction from a layout, it is the technology framing. Most courses do some of both — the question is where the weight falls.

⚠ Course-code variation across Florida

VLSI design is taught at most Florida engineering programmes, under several numbers:

• EEE 4310 — UF and UWF.
• EEE 4334 Introduction to VLSI Design — University of Central Florida (requires EEE 3342C and EEE 3307C, each with a C or better).
• EEE 4313 CMOS Digital IC Design — FAMU and FSU.
• Graduate-level treatments appear as EEE 5315, EEE 5327 and EEE 6323.

SCNS equivalency does not cross course numbers. The content corresponds closely across these, but a receiving programme naming its prerequisites by number will not match them automatically. Carry the syllabus, and request a substitution early rather than in your final year.

⚠ UWF requires chemistry — an unusual prerequisite worth planning for

UWF’s prerequisite for EEE 4310 is (EEE 3308 and EEL 3701) and (CHM 2045 or CHM 1045 or CHM 1045C). The chemistry requirement is unusual for a circuits course and reflects the fabrication content — oxidation, diffusion and etching are chemical processes. Electrical engineering students who deferred their chemistry requirement can find themselves blocked from this course, sometimes discovering it only at registration. If you intend to take VLSI at UWF, clear the chemistry requirement early.

UF’s prerequisites are EEE 3308C and EEL 3701C — a first electronics course and a digital logic course. That combination is the substantive requirement in both cases: you need MOS device behaviour from electronics and Boolean/sequential design from digital logic simultaneously, and students weak in either meet the consequence quickly.

Position in the curriculum

EEE 4310 is a senior-level elective, taken after electronics and digital logic. It is the gateway to graduate VLSI study and to the physical-design and semiconductor career paths, and it is often the course that determines whether a student pursues integrated circuits at all. Where a programme offers a microelectronics concentration, this is normally its anchor.

Difficulty and time commitment

The conceptual content is manageable; the tool learning curve is what consumes the time. Cadence Virtuoso in particular is powerful and unforgiving, and a first layout that passes DRC and LVS commonly takes far longer than the design it represents. Plan on ten to twelve hours a week, weighted heavily toward tool work, and start layout assignments early — DRC and LVS errors cannot be rushed, and the failure mode is a long tail of small violations rather than one large problem.

The compensation is that this tool fluency is directly marketable. A student who can describe a full custom design taken through DRC, LVS and post-layout simulation has something concrete to discuss in an interview, and employers know what it costs to acquire.

Articulation and transfer

SCNS records EEE 4310 as guaranteed to transfer to an institution offering the same course, and two institutions carry it, both at 3 credits. The course is upper-division and carries no general-education or Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam covers digital systems and electronics including semiconductor materials and devices, but does not test VLSI design or layout specifically. This course is not primarily FE preparation — its device-physics and CMOS logic content supports the relevant FE topics indirectly, and students taking it should not treat it as a substitute for focused review.

AI Integration

Semiconductor design is one of the fields where machine learning has been genuinely adopted in the professional tool flow, which makes this more than a cautionary section.

Where AI is genuinely used in the discipline. Commercial EDA vendors ship reinforcement-learning-based placement and routing (Synopsys DSO.ai, Cadence Cerebrus), and design-space exploration, timing closure and analogue sizing all now use learned optimisation in production flows. Machine learning is also used in yield prediction and defect classification in fabrication. A student entering this field will use AI-assisted tools professionally, and that is a reason to understand what they optimise rather than a reason to avoid them.

Where a general-purpose assistant helps. Explaining logical effort, walking through a noise-margin derivation, generating SPICE decks and parameter sweeps, writing Tcl or SKILL scripts for tool automation, and interpreting the notoriously cryptic DRC and LVS error messages — which is a real and substantial time saving for a beginner.

⚠ Where it fails, and why it coincides with this course’s subject. The characteristic error is that a model answers with process-independent numbers — quoting a propagation delay, a threshold voltage or a power figure without reference to the node, supply voltage, temperature or load. That is exactly the mistake this course exists to eliminate. The entire point of a technology-aware design course is that a circuit’s behaviour is a property of the process it is built in, not of its schematic: the same inverter has a different switching threshold, different delay and radically different leakage at 180 nm and at 7 nm. A confident number with no PDK behind it is not an answer.

Two further failures are worth naming. Models will produce layouts and design rules that do not correspond to any real PDK, mixing lambda-based teaching rules with micron-based foundry rules. And they consistently underweight parasitics — giving pre-layout answers to post-layout questions, which is the single most common way a student design passes simulation and fails in silicon.

The engineer’s responsibility. In integrated circuit design the verification chain is the deliverable: DRC, LVS, and post-layout simulation with extracted parasitics. A design is not correct because it looks correct or because a tool proposed it; it is correct because it passed signoff against a specific process. Tape-out is expensive and irreversible, which is why this discipline is stricter than most about evidence.

Academic integrity. The University of Florida Student Honor Code and UWF’s academic integrity policy both cover AI-generated work. Layout and design assignments are normally expected to be individual work even where scripting assistance is permitted, and submitting a layout you did not construct is straightforwardly a violation. Ask your instructor what is allowed before you rely on a tool, and disclose its use where the syllabus requires it.