EEE3342C: Digital Systems

Course Description

EEE 3342C Digital Systems is the introductory digital logic course in the electrical and computer engineering curriculum at the University of Central Florida. It is the point at which a student stops analysing continuous voltages and currents and starts designing with discrete logic: Boolean algebra, gates, combinational blocks, flip-flops, finite state machines, and the programmable devices those designs are actually built on. Nearly everything downstream in computer engineering — computer organisation, VLSI design, embedded systems, hardware description languages, hardware security — assumes this material.

The Statewide Course Numbering System files EEE3342C under the title Introduction to Digital Circuits and Systems and describes it as “switching theory and devices; combinational and sequential logic; logic design using standard components such as ROM, arithmetic units, multiplexers, registers, and counters.” UCF’s own catalog description is narrower in wording but the same course: “combinational and sequential logic circuits including registers, arithmetic units, memories, finite state machines, and design with programmable logic devices.” The two agree, and the guide below is written to both.

UCF is the only Florida institution that offers this course number. That is not a sign that the subject is rare — introductory digital logic is a required course in every electrical and computer engineering programme in the state. It is a numbering fact, and an important one: UCF files the course under the EEE prefix while every other Florida institution files the same subject under EEL or CDA. The Special Information section below sets out what that means for transfer, and it is the single most consequential thing on this page.

The C suffix is real here. UCF schedules a laboratory alongside the lecture, and the course carries a material and supply fee. Students design, simulate and physically realise logic on programmable hardware rather than only working problems on paper.

Learning Outcomes

Required Outcomes

• Represent numeric data in binary, octal, hexadecimal and BCD, convert between them, and perform arithmetic including two’s-complement addition and subtraction with correct detection of overflow.
• Apply the postulates and theorems of Boolean algebra and DeMorgan’s laws to manipulate and simplify switching functions.
• Minimise combinational logic functions using Karnaugh maps, including don’t-care conditions, and recognise when a tabular or software method is required instead.
• Analyse a given combinational circuit to recover its truth table and function, and synthesise a circuit from a written specification.
• Design with standard combinational building blocks — multiplexers, decoders, encoders, comparators, adders and arithmetic units — rather than only with discrete gates.
• Explain the operation of latches and flip-flops (SR, D, JK, T), including clocking, setup and hold requirements, and the difference between level-sensitive and edge-triggered behaviour.
• Analyse sequential circuits to produce state tables and state diagrams, and synthesise a synchronous sequential circuit from a state diagram using any flip-flop type.
• Design registers, shift registers and counters, both from standard parts and from first principles.
• Model a finite state machine in Moore and Mealy form and choose appropriately between them.
• Implement a working design on programmable logic and verify it against its specification in the laboratory.

Optional Outcomes

• Write synthesisable hardware description language (Verilog or VHDL) for combinational and sequential blocks. UCF treats HDL more fully in later coursework, so the depth reached here varies with the instructor.
• Perform state minimisation and state assignment, and evaluate the effect of assignment on the resulting logic.
• Analyse static and dynamic hazards in combinational logic and design to avoid them.
• Compare logic families and interpret device datasheet parameters such as fan-out, noise margin and propagation delay.
• Describe memory organisation — ROM, RAM, and the use of ROM as a logic element.
• Build a simple datapath-and-controller partition as a bridge toward computer organisation.

Major Topics

Required Topics

• Number systems and codes — positional notation, base conversion, signed representations, two’s complement, BCD, Gray code, character codes.
• Switching algebra — Boolean postulates and theorems, DeMorgan’s laws, canonical sum-of-products and product-of-sums, minterms and maxterms.
• Logic gates and switching devices — AND, OR, NOT, NAND, NOR, XOR; universal gates; positive and negative logic conventions.
• Combinational minimisation — Karnaugh maps to five or six variables, prime implicants, essential prime implicants, don’t-cares, two-level and multi-level realisations.
• Combinational building blocks — multiplexers and demultiplexers, decoders and encoders, priority encoders, magnitude comparators.
• Arithmetic units — half and full adders, ripple-carry and carry-lookahead adders, subtractors, and an introduction to multiplication hardware.
• Latches and flip-flops — SR latch, gated latch, D, JK and T flip-flops, characteristic and excitation tables, timing parameters.
• Sequential analysis — state tables, state diagrams, timing diagrams, Moore and Mealy machines.
• Sequential synthesis — state assignment, excitation equations, next-state and output logic, self-starting design.
• Registers and counters — parallel and shift registers, synchronous and asynchronous (ripple) counters, modulo-N counters, ring and Johnson counters.
• Memory elements — ROM, PROM, RAM organisation; ROM as a means of implementing arbitrary combinational logic.
• Programmable logic — PLA, PAL and CPLD/FPGA structure, and the design flow from specification through synthesis to a configured device.

Optional Topics

• Hardware description languages — Verilog or VHDL syntax for structural and behavioural modelling, testbenches and simulation.
• Quine–McCluskey tabular minimisation and computer-aided minimisation for functions too large for a Karnaugh map.
• Hazards, races and glitches; asynchronous sequential circuits.
• Metastability and the discipline of synchronising asynchronous inputs.
• Logic families — TTL and CMOS characteristics, interfacing, power and delay trade-offs.
• Algorithmic state machine (ASM) charts and datapath/controller partitioning.
• Arithmetic logic unit design as a capstone laboratory exercise.

Resources & Tools

• Digital Design and Computer Architecture (Harris and Harris) and Digital Design: With an Introduction to the Verilog HDL (Mano and Ciletti) are the two texts most commonly adopted for this level in Florida programmes; Fundamentals of Logic Design (Roth and Kinney) and Digital Design: Principles and Practices (Wakerly) also appear.
• Logic simulation and schematic capture — Logisim Evolution and Multisim are widely used for early combinational and sequential exercises because they make the truth table and the waveform visible side by side.
• FPGA and CPLD design suites — Xilinx/AMD Vivado and Intel Quartus Prime, both free in their student or Lite editions. These carry the design from HDL or schematic through synthesis, placement and routing to a bitstream.
• Development boards — Digilent Basys 3, Nexys A7 and similar Artix-7 boards are the common laboratory platform; older laboratories may still use discrete 7400-series TTL on breadboards, which teaches fan-out and noise margin in a way simulation does not.
• Laboratory instruments — digital oscilloscope, logic analyser, function generator and bench power supply. Reading a logic analyser trace against an expected timing diagram is a core skill.
• Standards and reference material — IEEE Std 91/91a for logic symbols, IEEE Std 1364 (Verilog) and IEEE Std 1076 (VHDL), and manufacturer datasheets from Texas Instruments and ON Semiconductor.
• UCF’s Department of Electrical and Computer Engineering publishes laboratory manuals for its ECE courses, and the course carries a material and supply fee covering laboratory consumables.

Career Pathways

• Digital design engineer and FPGA engineer (SOC 17-2061, Computer Hardware Engineers) — the most direct line from this course.
• Computer hardware engineer (SOC 17-2061) and electrical engineer (SOC 17-2071), the two occupations most UCF ECE graduates enter.
• Embedded systems engineer — digital logic plus microcontroller work is the standard combination for firmware and hardware-adjacent roles.
• Verification engineer — UCF runs a dedicated course in this area (EEE 4701 Verification and Validation of Digital Systems), and this course is its foundation.
• Test engineer and hardware applications engineer in semiconductor and defence electronics.
• Florida employers who hire directly into these roles include Lockheed Martin (Orlando, missiles and fire control — the largest single employer of UCF electrical and computer engineering graduates), L3Harris (Melbourne and Palm Bay), Northrop Grumman (Melbourne), Siemens Energy (Orlando), Mitsubishi Power (Orlando), Leidos, SAIC and the simulation and training cluster in Orlando’s Central Florida Research Park, which sits adjacent to the UCF campus and is unusually accessible to students seeking internships.
• The Space Coast — Blue Origin, SpaceX, Boeing and Amazon Kuiper in Brevard County — recruits heavily for avionics and flight-hardware digital design.

Special Information

⚠⚠ Course-code variation across Florida — read this before transferring

UCF is the only Florida institution that numbers its introductory digital logic course EEE 3342C. Every other public university in the state files the same subject under a different prefix and number:

• EEL 3705 — Florida State University and Florida A&M University (Digital Logic Design, with a separate EEL 3705L laboratory), and the University of South Florida (Fundamentals of Digital Circuits, with EEL 3705L).
• EEL 3701 — the University of North Florida and the University of West Florida (Introduction to Digital Systems / Digital Logic and Computer Systems, each with a separate EEL 3701L); the University of Florida carries the integrated EEL 3701C Digital Logic & Computer Systems at 4 credits.
• EEL 3712 — Florida International University (Logic Design I, with EEL 3712L).
• EEL 3702 — Florida Polytechnic University (Digital Logic Design, with EEL 3702L).
• CDA 3201C and CDA 3203 — Florida Atlantic University; CDA 3200 — Florida Gulf Coast University.

Why this matters more than an ordinary title difference. SCNS equivalency does not cross course numbers. A receiving programme names its prerequisites by number — a UCF student who transfers to UF with EEE 3342C on the transcript does not automatically satisfy a requirement written as “EEL 3701C,” and a student arriving at UCF with EEL 3705 does not automatically satisfy one written as “EEE 3342C.” The credit transfers; the requirement match is what breaks. This is the failure mode that surfaces at a degree audit rather than at admission, which is what makes it expensive.

What to do about it. Keep the syllabus. Where the course content plainly corresponds, departments routinely approve a substitution, but the substitution has to be requested and it is granted on the strength of a syllabus, not a course number. Raise it with an academic advisor in the term you transfer, not in your final year.

Credit structure and the C suffix

UCF carries EEE 3342C at 3 credits with a scheduled laboratory, which is why the number carries the C suffix for an integrated lecture-plus-laboratory course. Expect roughly five contact hours a week across lecture and laboratory — noticeably more scheduled time than the 3-credit value suggests, which is the usual trap with C courses. A material and supply fee is assessed.

Several institutions package the same material as a separate lecture and laboratory pair (EEL 3705 + EEL 3705L, EEL 3701 + EEL 3701L). Three consequences follow if you move between the two packagings: the credit count differs (3 against 3+1 = 4), you receive one grade instead of two, and at the split institutions you must register for both halves — they are ordinarily co-requisites of each other and neither can be taken alone.

Prerequisites

UCF’s catalog lists a single course prerequisite: EGN 3211 Engineering Analysis and Computation, with a minimum grade of C. The statewide SCNS record carries a broader gate — MAC 2311, MAC 2312, MAC 2313, PHY 2048 and PHY 2049, or consent of instructor, with a C or better and a cumulative GPA of 2.7 — which reflects the mathematics and physics sequence an engineering student will have completed by this point regardless. Confirm the current requirement in the UCF catalog and with an ECE advisor, because EGN 3211 itself is restricted to Electrical Engineering, Computer Engineering, Materials Science & Engineering and Photonic Science & Engineering students.

That restriction is worth stating plainly: the prerequisite chain into EEE 3342C is closed to students outside those majors, so a student intending to take it needs to be in the major, or to have arranged instructor consent, well before registration opens.

Position in the curriculum

EEE 3342C sits at the start of the digital sequence and is offered every semester, which gives some scheduling flexibility. It gates EEE 4334 Introduction to VLSI Design (which requires both EEE 3342C and EEE 3307C Electronics I, each with a C or better), and it is the assumed background for UCF’s computer organisation, embedded systems, hardware description language and hardware security courses. Because so much depends on it, a weak grade here tends to be felt for several terms rather than one.

Difficulty and time commitment

The conceptual content is not mathematically heavy — there is no calculus in the core material — but it is unfamiliar, and the failure mode is procedural rather than theoretical. Students who treat Karnaugh maps and state assignment as recipes to memorise generally struggle at the point where a design must be specified from a written problem statement. Plan on eight to ten hours a week outside class, weighted toward laboratory work and debugging, and expect the debugging to take longer than the design.

Articulation and transfer

SCNS records EEE 3342C as guaranteed to transfer to an institution offering the same course — but as set out above, no other Florida institution offers this number, so the guarantee has little practical reach. Treat this as a course that will need a substitution review, and keep the documentation to support one.

The course is upper-division and is not part of the general-education core; it carries no Gordon Rule designation.

FE exam relevance

The NCEES Fundamentals of Engineering (Electrical and Computer) exam includes a Digital Systems topic area covering number systems, Boolean logic, logic gates, combinational and sequential circuits, and state machines — and a related Computer Systems area. This course is the primary preparation for that portion of the exam. Students planning to sit the FE in their senior year should keep their notes from this course rather than relying on a review manual alone; the FE tests the same material at roughly the same depth.

AI Integration

Digital design is one of the areas where AI assistance has moved quickly, and where the failure modes are unusually easy to demonstrate — which makes it a useful place to learn the habit of verification.

Where it helps. Large language models are competent at explaining Karnaugh map reductions step by step, at translating a written specification into a first-draft state diagram, at generating HDL testbench scaffolding, and at explaining synthesis tool error messages, which are notoriously opaque for beginners. Commercial EDA tools now embed AI features for design-space exploration and timing closure, and the semiconductor industry uses machine learning in placement and routing routinely.

⚠ Where it fails, and why it matters here. Generated HDL frequently simulates correctly and synthesises to something quite different from what was intended — inferred latches from incomplete sensitivity lists or missing else branches, blocking assignments used where non-blocking are required, and combinational loops. These are precisely the mistakes the course exists to teach you to avoid, and they do not announce themselves: the code looks reasonable, the simulation passes, and the fault appears in hardware as an intermittent timing failure. A model will also produce a Karnaugh map reduction with confident but incorrect grouping, because the visual adjacency that makes the method work is not something a text model handles reliably.

The engineer’s responsibility. A digital design is verified against its specification by simulation and by measurement, not by the plausibility of the code that produced it. If you cannot derive the truth table or the state table yourself, you cannot tell whether the generated design is right — and in this course the truth table is the deliverable, not the code.

Academic integrity. UCF’s Rules of Conduct on academic misconduct apply to AI-generated work. Policy varies by instructor and by assignment, and laboratory reports are often treated differently from design assignments. Ask what is permitted before you use a tool, and disclose its use where the syllabus requires it.