Programmable Digital Devices and Lab

Course Description

Programmable Digital Devices and Lab covers the architecture and applications of various types of programmable logic devices and design entry methods — hardware description language, schematic capture, and others, with lab exercises using PALs, PLDs, and FPGAs.

Within the SCNS taxonomy, CET is the Computer Engineering Technology prefix and the C suffix marks a combined lecture-and-laboratory course. Daytona State publishes this at 3 credits, offered spring, with CET3198 and CET3198L as prerequisites, giving approximately 60 contact hours at the prefix's three-credit C-form convention.

This completes the digital design sequence, and its subject is the technology that made modern digital design possible. A field-programmable gate array lets a designer implement a substantial digital system in hours rather than committing to a fabricated chip, which is why FPGAs are used everywhere from prototyping to production in aerospace, defence, telecommunications, and instrumentation — all sectors with a significant Florida presence.

Daytona State does not publish a lecture and laboratory split for its CET courses. The prefix's three-credit C-suffixed courses run at approximately 20 contact hours per credit — CET1123C, CET1179C, CET1610C, CET2123C, CET2179C, CET2620C, CET2660C, CET2688C, CET2880C, CET2881C, CET2883C, CET2890C, CET2892C and CET2930C are all published at 3 credits and 60 hours. This course is priced at that convention.

Learning Outcomes

Required Outcomes

• Describe the architecture of programmable logic devices.
• Compare PALs, PLDs, CPLDs and FPGAs and describe their appropriate uses.
• Describe FPGA internal architecture: logic blocks, interconnect, and I/O.
• Describe look-up tables and how they implement logic.
• Describe embedded resources: block memory, DSP blocks, and clock management.
• Describe configuration and programming technologies and their trade-offs.
• Select a device appropriate to a design's requirements.
• Apply hardware description language design entry.
• Apply schematic capture design entry and compare it with HDL.
• Use intellectual property cores and vendor-supplied modules.
• Manage a design project through the vendor toolchain.
• Synthesise a design and interpret synthesis and utilisation reports.
• Perform place and route and interpret the results.
• Write timing constraints for a design.
• Perform static timing analysis and close timing on a design.
• Diagnose and resolve timing violations.
• Apply clock domain crossing techniques safely.
• Design and implement a substantial digital system on an FPGA.
• Implement interfaces to external devices and peripherals.
• Verify a design in simulation and on hardware.
• Use on-chip debugging tools to observe internal signals.
• Optimise a design for area, speed, or power.
• Document a design to a professional standard.
• Present and defend a completed design project.

Optional Outcomes

• Describe soft processor cores and embedded system design on FPGA.
• Describe high-level synthesis approaches.
• Describe partial reconfiguration.
• Describe ASIC design flow and its relationship to FPGA design.
• Implement a digital signal processing function on an FPGA.
• Complete an independent capstone hardware project.

Major Topics

Required Topics

• Programmable logic architecture
• PALs, PLDs, CPLDs and FPGAs
• FPGA internal architecture
• Look-up tables
• Embedded resources
• Configuration technologies
• Device selection
• HDL design entry
• Schematic capture entry
• IP cores and vendor modules
• Toolchain project management
• Synthesis and utilisation reports
• Place and route
• Timing constraints
• Static timing analysis
• Resolving timing violations
• Clock domain crossing
• System design on FPGA
• External interfacing
• Simulation and hardware verification
• On-chip debugging
• Optimisation for area, speed and power
• Design documentation
• Project presentation

Optional Topics

• Soft processor cores and embedded design
• High-level synthesis
• Partial reconfiguration
• ASIC design flow
• DSP on FPGA
• Capstone hardware project

Resources & Tools

• The programme's laboratory and its isolated network — the only place you can lawfully practise most of this. Use every scheduled hour and every open-lab hour.
• Virtualisation software — VirtualBox is free, VMware Workstation Player is free for personal use; a home lab of virtual machines costs nothing but disk space.
• Kali Linux and the SANS SIFT Workstation — free tool distributions for security testing and forensics respectively.
• Autopsy and The Sleuth Kit (sleuthkit.org) — free and open-source forensic tools used professionally, not merely for teaching.
• NIST Computer Forensics Tool Testing programme (cftt.nist.gov) — free tool validation reports; the reference when you need to defend a tool choice.
• NIST Special Publications, especially SP 800-86 (forensic techniques in incident response) and SP 800-61 (incident handling) — free, authoritative, and directly examinable.
• CISA (cisa.gov) — free advisories, guidance, and free training resources.
• MITRE ATT&CK (attack.mitre.org) — free; the standard framework for describing adversary behaviour, and increasingly expected knowledge.
• TryHackMe, Hack The Box, and OverTheWire — lawful practice environments, with free tiers; the right place to practise offensive technique.
• CompTIA and Cisco Networking Academy materials — aligned to the certifications employers ask for.
• Xilinx Vivado and Intel Quartus Prime — free editions support the devices used in most teaching boards; install one at home and build outside lab hours.
• Your device family's user guide and datasheet — vendor documentation is the authority on architecture and constraints, and learning to read it is part of the professional skill.
• FPGA Prototyping by VHDL Examples (Chu) — worked designs at exactly this level.
• A personal FPGA board — entry-level boards are inexpensive, and a documented personal project is the strongest thing you can show an employer in this field.

Career Pathways

• Information security analyst — SOC 15-1212; consistently among the fastest-growing occupations.
• Computer network support specialist — SOC 15-1231; computer user support specialist — SOC 15-1232.
• Network and computer systems administrator — SOC 15-1244.
• Digital forensics examiner — in law enforcement, in corporate investigations, and in consulting firms.
• Incident responder and security operations centre analyst — a large and growing entry route into security.
• Electrical and electronics engineering technologist or technician — SOC 17-3023, for the digital design pathway.
• Embedded systems and FPGA development — a specialised, well-paid pathway from the digital design sequence.
• Florida's defence, space, and simulation sector — the Space Coast, Orlando's simulation and training cluster, and Tampa's defence presence all hire heavily in these areas, and many roles require U.S. citizenship and a security clearance.
• Public sector and law enforcement — state and county agencies, and federal offices with a large Florida presence.
• Healthcare, financial services, and hospitality IT — all large Florida sectors with substantial compliance-driven security demand.
• Consulting and managed security service providers.
• ⚠ Many security and forensics roles require a clean background — criminal history, and for cleared work significant unresolved debt or foreign contacts, can be disqualifying. Find this out before investing in the pathway.

Special Information

⚠ Timing closure is the professional skill this course develops

• A design that is functionally correct but fails timing does not work, and getting from one to the other is most of what an FPGA engineer actually does.
• Write your constraints properly. An unconstrained design reports no timing violations because nothing was checked — which is the most dangerous kind of clean report.
• Read the timing report, not just the pass or fail. The critical path tells you where the design is slow and what to restructure.
• Long combinational paths are the usual cause. Adding a pipeline register frequently fixes timing at the cost of a cycle of latency, and knowing when that trade is acceptable is design judgement.
• Clock domain crossings need explicit synchronisation. Passing a signal between domains without a synchroniser produces metastability and intermittent failures that survive every test you run — and appear in the field.
• Check the utilisation report as well as timing; a design at ninety-five percent utilisation becomes hard to route and hard to modify.
• Use the on-chip debug tools. Being able to capture internal signals on live hardware is a genuine professional skill and it is far quicker than guessing.
• Simulate first, always. Debugging on hardware what you could have caught in simulation wastes hours.
• Version-control your design. Toolchain projects generate many files; keep the sources and the constraints, and know which generated outputs can be rebuilt.

⚠ Certifications carry real weight in this field — more than in most

• Information technology and security hire on demonstrated capability, and certifications are the common shorthand for it — frequently appearing as hard requirements in job postings and in government and contractor roles.
• Foundational: CompTIA A+ (hardware and operating systems), Network+, and Security+. Security+ in particular satisfies a widely cited U.S. Department of Defense baseline requirement, which makes it valuable in Florida's substantial defence and contractor sector.
• Networking: Cisco CCNA remains the recognised entry credential.
• Digital forensics: EnCE (EnCase), ACE (AccessData), CCE, and the SANS GCFE and GCFA. The SANS credentials are the most respected and by far the most expensive — employers frequently pay for them, so raise it at interview rather than self-funding.
• Security management: CISSP is the senior standard but requires several years of documented experience; SSCP is its practitioner-level counterpart and is reachable earlier.
• Time your certification to your coursework. Sit the examination while the material is fresh — pass rates fall sharply the longer graduates wait.
• Certifications expire. Most require continuing education and renewal, so plan for the ongoing cost.
• ⚠ A certification is not a substitute for the degree, and the degree is not a substitute for certifications. Employers in this field commonly want both, plus evidence you have actually built and broken things.
• Build a home lab and document it. Virtual machines cost nothing, and a candidate who can describe what they built and what went wrong interviews far better than one who lists courses.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement.

⚠ That boundary is live in this prefix. Daytona State offers CET courses at the 1000, 2000, 3000 and 4000 levels, the upper-division ones forming part of a bachelor of applied science. A 2000-level CET course does not substitute for its 3000- or 4000-level counterpart even where the subject matter overlaps — compare CET2880C/CET2881C (Data Forensics I and II, lower division) with CET4860/CET4861 (Introduction to and Advanced Digital Forensics, upper division). Confirm with an advisor which lower-division courses feed the BAS.

CET4138C is 3 credits and approximately 60 contact hours, offered spring at Daytona State, with CET3198 and CET3198L as prerequisites.

It completes the digital design sequence — CET3116 → CET3198 + CET3198L → CET4138C. See also CET4190C (Applied Digital Signal Processing) and CET4542 (Computer Architecture).