Digital Systems Lab

Course Description

Digital Systems Lab is the hands-on lab component for VHDL programming; analysis, design and implementation of combinational circuits; analysis, design and implementation of sequential circuits using flip-flops; finite state machines; Mealy and Moore models; state tables and state graphs; reduction of state tables; and ASM charts.

Within the SCNS taxonomy, CET is the Computer Engineering Technology prefix and the L suffix marks a laboratory-only course, paired with the CET3198 lecture. Daytona State publishes this at 1 credit, offered fall, with CET3198 as corequisite, giving approximately 30 contact hours at the prefix's laboratory convention — the rate confirmed by CET1114L, also 1 credit and 30 hours.

The laboratory is where a design stops being a diagram and meets physical reality. Simulation is forgiving; hardware is not. Timing that was ideal in simulation becomes propagation delay, a pin assignment that looked arbitrary determines whether anything works, and a design that synthesises may still fail because the constraints were never written. That gap between simulation and implementation is the specific thing this laboratory teaches.

Learning Outcomes

Required Outcomes

• Use a hardware description language toolchain end to end.
• Create, organise, and manage a design project in the toolchain.
• Write synthesisable VHDL for combinational logic.
• Write synthesisable VHDL for sequential logic.
• Write test benches to exercise a design.
• Run behavioural simulation and interpret waveform output.
• Diagnose and correct functional faults from simulation.
• Synthesise a design and interpret synthesis reports.
• Assign pins and write constraints for a target device.
• Implement a design on programmable logic hardware.
• Verify a design's behaviour on hardware against its specification.
• Diagnose faults that appear only in hardware.
• Implement combinational circuits, including multiplexers and arithmetic units.
• Implement sequential circuits using flip-flops, counters and registers.
• Implement a finite state machine on hardware.
• Implement both Mealy and Moore forms and compare their behaviour.
• Implement a controller and datapath for a specified task.
• Interface a design with switches, displays and other board peripherals.
• Measure and interpret timing behaviour.
• Apply good laboratory practice with electronic equipment.
• Apply electrostatic discharge precautions.
• Maintain a laboratory notebook documenting each exercise.
• Work effectively with a laboratory partner.
• Present a working design and explain its operation.

Optional Outcomes

• Use an oscilloscope or logic analyser to observe signals.
• Implement a design using external components.
• Apply timing analysis tools to a design.
• Implement a communication interface such as UART or SPI.
• Optimise a design for area or speed.
• Complete an independent hardware project.

Major Topics

Required Topics

• Toolchain workflow
• Project creation and management
• Synthesisable combinational VHDL
• Synthesisable sequential VHDL
• Test bench construction
• Behavioural simulation and waveforms
• Functional fault diagnosis
• Synthesis and reports
• Pin assignment and constraints
• Hardware implementation
• Hardware verification
• Hardware-only fault diagnosis
• Combinational circuit implementation
• Sequential circuit implementation
• State machine implementation
• Mealy and Moore comparison
• Controller and datapath implementation
• Board peripheral interfacing
• Timing measurement
• Laboratory practice
• Electrostatic discharge precautions
• Laboratory notebook
• Working with a partner
• Presenting a working design

Optional Topics

• Oscilloscope and logic analyser use
• External component interfacing
• Timing analysis tools
• UART or SPI interfaces
• Area and speed optimisation
• Independent hardware project

Resources & Tools

• The programme's laboratory and its isolated network — the only place you can lawfully practise most of this. Use every scheduled hour and every open-lab hour.
• Virtualisation software — VirtualBox is free, VMware Workstation Player is free for personal use; a home lab of virtual machines costs nothing but disk space.
• Kali Linux and the SANS SIFT Workstation — free tool distributions for security testing and forensics respectively.
• Autopsy and The Sleuth Kit (sleuthkit.org) — free and open-source forensic tools used professionally, not merely for teaching.
• NIST Computer Forensics Tool Testing programme (cftt.nist.gov) — free tool validation reports; the reference when you need to defend a tool choice.
• NIST Special Publications, especially SP 800-86 (forensic techniques in incident response) and SP 800-61 (incident handling) — free, authoritative, and directly examinable.
• CISA (cisa.gov) — free advisories, guidance, and free training resources.
• MITRE ATT&CK (attack.mitre.org) — free; the standard framework for describing adversary behaviour, and increasingly expected knowledge.
• TryHackMe, Hack The Box, and OverTheWire — lawful practice environments, with free tiers; the right place to practise offensive technique.
• CompTIA and Cisco Networking Academy materials — aligned to the certifications employers ask for.
• Your board's documentation and constraints file — the most important document in this course, and the one students skip. Pin assignments come from it.
• RTL Hardware Design Using VHDL (Chu) — written around exactly this kind of laboratory work.

Career Pathways

• Information security analyst — SOC 15-1212; consistently among the fastest-growing occupations.
• Computer network support specialist — SOC 15-1231; computer user support specialist — SOC 15-1232.
• Network and computer systems administrator — SOC 15-1244.
• Digital forensics examiner — in law enforcement, in corporate investigations, and in consulting firms.
• Incident responder and security operations centre analyst — a large and growing entry route into security.
• Electrical and electronics engineering technologist or technician — SOC 17-3023, for the digital design pathway.
• Embedded systems and FPGA development — a specialised, well-paid pathway from the digital design sequence.
• Florida's defence, space, and simulation sector — the Space Coast, Orlando's simulation and training cluster, and Tampa's defence presence all hire heavily in these areas, and many roles require U.S. citizenship and a security clearance.
• Public sector and law enforcement — state and county agencies, and federal offices with a large Florida presence.
• Healthcare, financial services, and hospitality IT — all large Florida sectors with substantial compliance-driven security demand.
• Consulting and managed security service providers.
• ⚠ Many security and forensics roles require a clean background — criminal history, and for cleared work significant unresolved debt or foreign contacts, can be disqualifying. Find this out before investing in the pathway.

Special Information

⚠ Simulation passing is not the same as hardware working

• The gap between a passing simulation and a working board is where this laboratory's real content lives, and every student meets it.
• Check your constraints and pin assignments first when hardware misbehaves. The overwhelming majority of "my design works in simulation but not on the board" problems are pin assignment or constraint errors, not logic errors.
• Read the synthesis warnings. Inferred latches, unconnected signals, and truncated widths are reported clearly and ignored routinely, and each of them changes what the hardware does.
• An inferred latch is almost always a mistake — typically an incomplete if statement or case statement in a combinational process. Assign every output in every branch.
• Clocking discipline matters. Use a single clock edge, avoid gated clocks, and synchronise any external input before using it — asynchronous inputs cause metastability and intermittent, maddening failures.
• Debounce mechanical switches. A button press is not one clean edge, and a counter that jumps by seven is usually this.
• Test incrementally. Get a small piece working on hardware before building the whole design; debugging a large untested design on a board is genuinely painful.
• Keep a proper notebook — what you built, what failed, what fixed it. It is assessed, and it is how you avoid solving the same problem twice.
• Handle boards carefully. Power off before rewiring, observe electrostatic discharge precautions, and never force a connector.

⚠ Certifications carry real weight in this field — more than in most

• Information technology and security hire on demonstrated capability, and certifications are the common shorthand for it — frequently appearing as hard requirements in job postings and in government and contractor roles.
• Foundational: CompTIA A+ (hardware and operating systems), Network+, and Security+. Security+ in particular satisfies a widely cited U.S. Department of Defense baseline requirement, which makes it valuable in Florida's substantial defence and contractor sector.
• Networking: Cisco CCNA remains the recognised entry credential.
• Digital forensics: EnCE (EnCase), ACE (AccessData), CCE, and the SANS GCFE and GCFA. The SANS credentials are the most respected and by far the most expensive — employers frequently pay for them, so raise it at interview rather than self-funding.
• Security management: CISSP is the senior standard but requires several years of documented experience; SSCP is its practitioner-level counterpart and is reachable earlier.
• Time your certification to your coursework. Sit the examination while the material is fresh — pass rates fall sharply the longer graduates wait.
• Certifications expire. Most require continuing education and renewal, so plan for the ongoing cost.
• ⚠ A certification is not a substitute for the degree, and the degree is not a substitute for certifications. Employers in this field commonly want both, plus evidence you have actually built and broken things.
• Build a home lab and document it. Virtual machines cost nothing, and a candidate who can describe what they built and what went wrong interviews far better than one who lists courses.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement.

⚠ That boundary is live in this prefix. Daytona State offers CET courses at the 1000, 2000, 3000 and 4000 levels, the upper-division ones forming part of a bachelor of applied science. A 2000-level CET course does not substitute for its 3000- or 4000-level counterpart even where the subject matter overlaps — compare CET2880C/CET2881C (Data Forensics I and II, lower division) with CET4860/CET4861 (Introduction to and Advanced Digital Forensics, upper division). Confirm with an advisor which lower-division courses feed the BAS.

CET3198L is 1 credit and approximately 30 contact hours, offered fall at Daytona State, with CET3198 as corequisite.

Under SCNS the L suffix is part of the course number, so CET3198 and CET3198L are distinct courses and a transfer bringing one does not satisfy the other. The sequence continues in CET4138C (Programmable Digital Devices and Lab).