Digital Systems

Course Description

Digital Systems covers VHDL programming; analysis, design and implementation of combinational circuits; analysis, design and implementation of sequential circuits using flip-flops; finite state machines; Mealy and Moore models; state tables and state graphs; reduction of state tables; and ASM charts, and includes a collaborative group project.

Within the SCNS taxonomy, CET is the Computer Engineering Technology prefix. Daytona State publishes this at 2 credits, offered fall, with CET3116 or CET1112C plus MAD2104 or COT3100 as prerequisites and CET3198L as corequisite, giving approximately 30 contact hours at the prefix's unsuffixed convention.

The discrete mathematics prerequisite is the signal for what this course actually is. Finite state machines are a formal model, and designing with them is mathematical work — specifying states, transitions, and outputs precisely, then reducing the specification before implementing it. This is where digital design stops being circuit assembly and becomes system specification, and it is the most transferable content in the sequence.

Daytona State does not publish a lecture and laboratory split for its CET courses. The prefix's unsuffixed courses run consistently at 15 contact hours per credit — CET1588, CET2544, CET2691, CET2792, CET2793, CET2794, CET3505 and CET4542 are all published at 3 credits and 45 hours, without exception. Its C-suffixed courses run at 20 or above and its L-suffixed laboratories at 30. This course is unsuffixed and is priced at the unsuffixed convention.

Learning Outcomes

Required Outcomes

• Write VHDL to describe combinational logic.
• Write VHDL to describe sequential logic using processes and clocking.
• Describe VHDL entities, architectures, and structural composition.
• Describe signal and variable semantics and their differences.
• Analyse a combinational circuit and derive its function.
• Design a combinational circuit from a specification and implement it.
• Analyse a sequential circuit using flip-flops.
• Design a sequential circuit from a specification and implement it.
• Describe finite state machines and their formal components.
• Distinguish Mealy and Moore models and select appropriately.
• Construct a state table from a problem specification.
• Construct a state graph and relate it to the state table.
• Reduce a state table by identifying equivalent states.
• Perform state assignment and describe its effect on implementation.
• Construct ASM charts and relate them to state machines.
• Implement a finite state machine in VHDL.
• Design a controller and datapath for a specified task.
• Write a test bench to verify a design.
• Simulate a design and interpret waveform output.
• Diagnose faults in a design from simulation results.
• Describe timing constraints and their effect on a design.
• Document a design so another engineer can follow it.
• Work effectively on a collaborative design project.
• Present and defend a design decision.

Optional Outcomes

• Describe pipelining and its effect on throughput.
• Describe metastability and synchroniser design.
• Apply formal verification concepts.
• Describe low-power design techniques.
• Implement a design on an FPGA board.
• Describe processor datapath design at an introductory level.

Major Topics

Required Topics

• VHDL for combinational logic
• VHDL for sequential logic
• Entities, architectures, and structure
• Signals versus variables
• Combinational analysis
• Combinational design and implementation
• Sequential analysis
• Sequential design and implementation
• Finite state machines
• Mealy and Moore models
• State tables
• State graphs
• State table reduction
• State assignment
• ASM charts
• Implementing state machines in VHDL
• Controller and datapath design
• Test benches
• Simulation and waveforms
• Fault diagnosis from simulation
• Timing constraints
• Design documentation
• Collaborative project work
• Presenting and defending design decisions

Optional Topics

• Pipelining
• Metastability and synchronisers
• Formal verification
• Low-power design
• FPGA implementation
• Introductory processor datapath

Resources & Tools

• The programme's laboratory and its isolated network — the only place you can lawfully practise most of this. Use every scheduled hour and every open-lab hour.
• Virtualisation software — VirtualBox is free, VMware Workstation Player is free for personal use; a home lab of virtual machines costs nothing but disk space.
• Kali Linux and the SANS SIFT Workstation — free tool distributions for security testing and forensics respectively.
• Autopsy and The Sleuth Kit (sleuthkit.org) — free and open-source forensic tools used professionally, not merely for teaching.
• NIST Computer Forensics Tool Testing programme (cftt.nist.gov) — free tool validation reports; the reference when you need to defend a tool choice.
• NIST Special Publications, especially SP 800-86 (forensic techniques in incident response) and SP 800-61 (incident handling) — free, authoritative, and directly examinable.
• CISA (cisa.gov) — free advisories, guidance, and free training resources.
• MITRE ATT&CK (attack.mitre.org) — free; the standard framework for describing adversary behaviour, and increasingly expected knowledge.
• TryHackMe, Hack The Box, and OverTheWire — lawful practice environments, with free tiers; the right place to practise offensive technique.
• CompTIA and Cisco Networking Academy materials — aligned to the certifications employers ask for.
• Fundamentals of Logic Design (Roth & Kinney) — covers state machines, ASM charts, and VHDL in exactly this order.
• RTL Hardware Design Using VHDL (Chu) — the book that teaches VHDL as hardware description rather than as programming.
• Xilinx Vivado or Intel Quartus Prime — free editions; simulate and synthesise your own designs outside lab hours.

Career Pathways

• Information security analyst — SOC 15-1212; consistently among the fastest-growing occupations.
• Computer network support specialist — SOC 15-1231; computer user support specialist — SOC 15-1232.
• Network and computer systems administrator — SOC 15-1244.
• Digital forensics examiner — in law enforcement, in corporate investigations, and in consulting firms.
• Incident responder and security operations centre analyst — a large and growing entry route into security.
• Electrical and electronics engineering technologist or technician — SOC 17-3023, for the digital design pathway.
• Embedded systems and FPGA development — a specialised, well-paid pathway from the digital design sequence.
• Florida's defence, space, and simulation sector — the Space Coast, Orlando's simulation and training cluster, and Tampa's defence presence all hire heavily in these areas, and many roles require U.S. citizenship and a security clearance.
• Public sector and law enforcement — state and county agencies, and federal offices with a large Florida presence.
• Healthcare, financial services, and hospitality IT — all large Florida sectors with substantial compliance-driven security demand.
• Consulting and managed security service providers.
• ⚠ Many security and forensics roles require a clean background — criminal history, and for cleared work significant unresolved debt or foreign contacts, can be disqualifying. Find this out before investing in the pathway.

Special Information

⚠ VHDL describes hardware — it is not a program, and treating it as one is the standard failure

• Everything in a VHDL architecture happens concurrently unless you are inside a process, and a student who reads it top to bottom like a script will produce designs that simulate strangely or will not synthesise at all.
• Ask what hardware each construct produces. If you cannot say what gates or registers a line describes, you are writing software, not a design.
• Signals are wires and update at the end of a process; variables update immediately. Confusing the two is the most common source of behaviour that looks like a simulator bug and is not.
• Not everything synthesisable is simulatable and vice versa. Delays and file operations belong in test benches, never in a design intended for hardware.
• Write the test bench before or alongside the design. Specifying what correct behaviour looks like clarifies the design and is what professionals do.
• Simulate at every stage. Debugging a large design that has never been simulated is far harder than debugging incrementally.
• Draw the state machine before writing any code. States, transitions, and outputs on paper first — coding an unclear state machine produces an unclear state machine.
• Reduce the state table before implementing. Equivalent states cost registers and logic for nothing.

⚠ Certifications carry real weight in this field — more than in most

• Information technology and security hire on demonstrated capability, and certifications are the common shorthand for it — frequently appearing as hard requirements in job postings and in government and contractor roles.
• Foundational: CompTIA A+ (hardware and operating systems), Network+, and Security+. Security+ in particular satisfies a widely cited U.S. Department of Defense baseline requirement, which makes it valuable in Florida's substantial defence and contractor sector.
• Networking: Cisco CCNA remains the recognised entry credential.
• Digital forensics: EnCE (EnCase), ACE (AccessData), CCE, and the SANS GCFE and GCFA. The SANS credentials are the most respected and by far the most expensive — employers frequently pay for them, so raise it at interview rather than self-funding.
• Security management: CISSP is the senior standard but requires several years of documented experience; SSCP is its practitioner-level counterpart and is reachable earlier.
• Time your certification to your coursework. Sit the examination while the material is fresh — pass rates fall sharply the longer graduates wait.
• Certifications expire. Most require continuing education and renewal, so plan for the ongoing cost.
• ⚠ A certification is not a substitute for the degree, and the degree is not a substitute for certifications. Employers in this field commonly want both, plus evidence you have actually built and broken things.
• Build a home lab and document it. Virtual machines cost nothing, and a candidate who can describe what they built and what went wrong interviews far better than one who lists courses.

How Florida course levels affect transfer

The first digit of an SCNS number denotes the year of offering, not transferability. Courses at the 1000 and 2000 levels transfer transparently between Florida public institutions, and 3000 to 4000 is unproblematic since both are upper division. The boundary that actually matters is 2000 to 3000, where lower-division credit generally cannot satisfy an upper-division requirement.

⚠ That boundary is live in this prefix. Daytona State offers CET courses at the 1000, 2000, 3000 and 4000 levels, the upper-division ones forming part of a bachelor of applied science. A 2000-level CET course does not substitute for its 3000- or 4000-level counterpart even where the subject matter overlaps — compare CET2880C/CET2881C (Data Forensics I and II, lower division) with CET4860/CET4861 (Introduction to and Advanced Digital Forensics, upper division). Confirm with an advisor which lower-division courses feed the BAS.

CET3198 is 2 credits and approximately 30 contact hours, offered fall at Daytona State, with CET3198L as a corequisite — distinct SCNS numbers, both required.

Note the flexible prerequisite: CET3116 or CET1112C satisfies the digital requirement, and MAD2104 or COT3100 the discrete mathematics requirement. The sequence continues in CET4138C.